interrupts.hh revision 3521:0b0b3551def0 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Kevin Lim
30 */
31
32#ifndef __ARCH_ALPHA_INTERRUPT_HH__
33#define __ARCH_ALPHA_INTERRUPT_HH__
34
35#include "arch/alpha/faults.hh"
36#include "arch/alpha/isa_traits.hh"
37#include "cpu/thread_context.hh"
38
39namespace AlphaISA
40{
41    class Interrupts
42    {
43      protected:
44        uint64_t interrupts[NumInterruptLevels];
45        uint64_t intstatus;
46
47      public:
48        Interrupts()
49        {
50            memset(interrupts, 0, sizeof(interrupts));
51            intstatus = 0;
52        }
53
54        void post(int int_num, int index)
55        {
56            DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
57
58            if (int_num < 0 || int_num >= NumInterruptLevels)
59                panic("int_num out of bounds\n");
60
61            if (index < 0 || index >= sizeof(uint64_t) * 8)
62                panic("int_num out of bounds\n");
63
64            interrupts[int_num] |= 1 << index;
65            intstatus |= (ULL(1) << int_num);
66        }
67
68        void clear(int int_num, int index)
69        {
70            DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
71
72            if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
73                panic("int_num out of bounds\n");
74
75            if (index < 0 || index >= sizeof(uint64_t) * 8)
76                panic("int_num out of bounds\n");
77
78            interrupts[int_num] &= ~(1 << index);
79            if (interrupts[int_num] == 0)
80                intstatus &= ~(ULL(1) << int_num);
81        }
82
83        void clear_all()
84        {
85            DPRINTF(Interrupt, "Interrupts all cleared\n");
86
87            memset(interrupts, 0, sizeof(interrupts));
88            intstatus = 0;
89        }
90
91        void serialize(std::ostream &os)
92        {
93            SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
94            SERIALIZE_SCALAR(intstatus);
95        }
96
97        void unserialize(Checkpoint *cp, const std::string &section)
98        {
99            UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
100            UNSERIALIZE_SCALAR(intstatus);
101        }
102
103        bool check_interrupts(ThreadContext * tc) const
104        {
105            return (intstatus != 0) && !(tc->readPC() & 0x3);
106        }
107
108        Fault getInterrupt(ThreadContext * tc)
109        {
110            int ipl = 0;
111            int summary = 0;
112
113            if (tc->readMiscReg(IPR_ASTRR))
114                panic("asynchronous traps not implemented\n");
115
116            if (tc->readMiscReg(IPR_SIRR)) {
117                for (int i = INTLEVEL_SOFTWARE_MIN;
118                     i < INTLEVEL_SOFTWARE_MAX; i++) {
119                    if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
120                        // See table 4-19 of 21164 hardware reference
121                        ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
122                        summary |= (ULL(1) << i);
123                    }
124                }
125            }
126
127            uint64_t interrupts = intstatus;
128            if (interrupts) {
129                for (int i = INTLEVEL_EXTERNAL_MIN;
130                    i < INTLEVEL_EXTERNAL_MAX; i++) {
131                    if (interrupts & (ULL(1) << i)) {
132                        // See table 4-19 of 21164 hardware reference
133                        ipl = i;
134                        summary |= (ULL(1) << i);
135                    }
136                }
137            }
138
139            if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
140                tc->setMiscReg(IPR_ISR, summary);
141                tc->setMiscReg(IPR_INTID, ipl);
142
143        /* The following needs to be added back in somehow */
144        // Checker needs to know these two registers were updated.
145/*#if USE_CHECKER
146        if (this->checker) {
147            this->checker->threadBase()->setMiscReg(IPR_ISR, summary);
148            this->checker->threadBase()->setMiscReg(IPR_INTID, ipl);
149        }
150#endif*/
151
152                DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
153                        tc->readMiscReg(IPR_IPLR), ipl, summary);
154
155                return new InterruptFault;
156            } else {
157                return NoFault;
158            }
159        }
160
161      private:
162    };
163}
164
165#endif
166
167