interrupts.hh revision 8232
12292SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 38707Sandreas.hansson@arm.com * All rights reserved. 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68707Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78707Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98707Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118707Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128707Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138707Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142727Sktlim@umich.edu * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272292SN/A * 282292SN/A * Authors: Steve Reinhardt 292292SN/A * Kevin Lim 302292SN/A */ 312292SN/A 322292SN/A#ifndef __ARCH_ALPHA_INTERRUPT_HH__ 332292SN/A#define __ARCH_ALPHA_INTERRUPT_HH__ 342292SN/A 352292SN/A#include "arch/alpha/faults.hh" 362292SN/A#include "arch/alpha/isa_traits.hh" 372292SN/A#include "base/compiler.hh" 382292SN/A#include "base/trace.hh" 392689Sktlim@umich.edu#include "cpu/thread_context.hh" 402689Sktlim@umich.edu#include "debug/Flow.hh" 412292SN/A#include "debug/Interrupt.hh" 422292SN/A#include "params/AlphaInterrupts.hh" 439944Smatt.horsnell@ARM.com#include "sim/sim_object.hh" 449944Smatt.horsnell@ARM.com 459944Smatt.horsnell@ARM.comnamespace AlphaISA { 462329SN/A 472980Sgblack@eecs.umich.educlass Interrupts : public SimObject 482329SN/A{ 492329SN/A private: 502292SN/A bool newInfoSet; 519444SAndreas.Sandberg@ARM.com int newIpl; 528232Snate@binkert.org int newSummary; 538232Snate@binkert.org BaseCPU * cpu; 548232Snate@binkert.org 556221Snate@binkert.org protected: 562292SN/A uint64_t interrupts[NumInterruptLevels]; 576221Snate@binkert.org uint64_t intstatus; 585529Snate@binkert.org 592292SN/A public: 605529Snate@binkert.org typedef AlphaInterruptsParams Params; 618707Sandreas.hansson@arm.com 624329Sktlim@umich.edu const Params * 634329Sktlim@umich.edu params() const 645529Snate@binkert.org { 652907Sktlim@umich.edu return dynamic_cast<const Params *>(_params); 662292SN/A } 679868Sjthestness@gmail.com 689868Sjthestness@gmail.com Interrupts(Params * p) : SimObject(p), cpu(NULL) 692292SN/A { 702292SN/A memset(interrupts, 0, sizeof(interrupts)); 712292SN/A intstatus = 0; 722980Sgblack@eecs.umich.edu newInfoSet = false; 732292SN/A } 742292SN/A 752292SN/A void 762292SN/A setCPU(BaseCPU * _cpu) 772292SN/A { 782292SN/A cpu = _cpu; 792292SN/A } 802292SN/A 812292SN/A void 822292SN/A post(int int_num, int index) 832292SN/A { 844329Sktlim@umich.edu DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 852292SN/A 862292SN/A if (int_num < 0 || int_num >= NumInterruptLevels) 872292SN/A panic("int_num out of bounds\n"); 882292SN/A 892292SN/A if (index < 0 || index >= (int)sizeof(uint64_t) * 8) 902292SN/A panic("int_num out of bounds\n"); 912292SN/A 924329Sktlim@umich.edu interrupts[int_num] |= 1 << index; 932292SN/A intstatus |= (ULL(1) << int_num); 948346Sksewell@umich.edu } 952292SN/A 962292SN/A void 972292SN/A clear(int int_num, int index) 982292SN/A { 992292SN/A DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 1002292SN/A 1012292SN/A if (int_num < 0 || int_num >= NumInterruptLevels) 1022292SN/A panic("int_num out of bounds\n"); 1032292SN/A 1042292SN/A if (index < 0 || index >= (int)sizeof(uint64_t) * 8) 1052292SN/A panic("int_num out of bounds\n"); 1062292SN/A 1074329Sktlim@umich.edu interrupts[int_num] &= ~(1 << index); 1082292SN/A if (interrupts[int_num] == 0) 1098346Sksewell@umich.edu intstatus &= ~(ULL(1) << int_num); 1102292SN/A } 1112292SN/A 1122292SN/A void 1132292SN/A clearAll() 1142292SN/A { 1152292SN/A DPRINTF(Interrupt, "Interrupts all cleared\n"); 1162292SN/A 1179868Sjthestness@gmail.com memset(interrupts, 0, sizeof(interrupts)); 1186221Snate@binkert.org intstatus = 0; 1194329Sktlim@umich.edu } 1204329Sktlim@umich.edu 1218850Sandreas.hansson@arm.com void 1222292SN/A serialize(std::ostream &os) 1232292SN/A { 1242292SN/A SERIALIZE_ARRAY(interrupts, NumInterruptLevels); 1252292SN/A SERIALIZE_SCALAR(intstatus); 1262292SN/A } 1272292SN/A 1282292SN/A void 1292292SN/A unserialize(Checkpoint *cp, const std::string §ion) 1302292SN/A { 1312292SN/A UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); 1322292SN/A UNSERIALIZE_SCALAR(intstatus); 1332292SN/A } 1342292SN/A 1352727Sktlim@umich.edu bool 1362727Sktlim@umich.edu checkInterrupts(ThreadContext *tc) const 1372727Sktlim@umich.edu { 1386221Snate@binkert.org return (intstatus != 0) && !(tc->pcState().pc() & 0x3); 1392727Sktlim@umich.edu } 1402727Sktlim@umich.edu 1412727Sktlim@umich.edu Fault 1422727Sktlim@umich.edu getInterrupt(ThreadContext *tc) 1432727Sktlim@umich.edu { 1442727Sktlim@umich.edu uint64_t ipl = 0; 1456221Snate@binkert.org uint64_t summary = 0; 1462292SN/A 1472292SN/A if (tc->readMiscRegNoEffect(IPR_ASTRR)) 1482292SN/A panic("asynchronous traps not implemented\n"); 1492292SN/A 1502292SN/A if (tc->readMiscRegNoEffect(IPR_SIRR)) { 1512292SN/A for (uint64_t i = INTLEVEL_SOFTWARE_MIN; 1522307SN/A i < INTLEVEL_SOFTWARE_MAX; i++) { 1539444SAndreas.Sandberg@ARM.com if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { 1542307SN/A // See table 4-19 of 21164 hardware reference 1559444SAndreas.Sandberg@ARM.com ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 1569444SAndreas.Sandberg@ARM.com summary |= (ULL(1) << i); 1579444SAndreas.Sandberg@ARM.com } 1589444SAndreas.Sandberg@ARM.com } 1599444SAndreas.Sandberg@ARM.com } 1609444SAndreas.Sandberg@ARM.com 1619444SAndreas.Sandberg@ARM.com uint64_t interrupts = intstatus; 1629444SAndreas.Sandberg@ARM.com if (interrupts) { 1639444SAndreas.Sandberg@ARM.com for (uint64_t i = INTLEVEL_EXTERNAL_MIN; 1649444SAndreas.Sandberg@ARM.com i < INTLEVEL_EXTERNAL_MAX; i++) { 1659444SAndreas.Sandberg@ARM.com if (interrupts & (ULL(1) << i)) { 1669444SAndreas.Sandberg@ARM.com // See table 4-19 of 21164 hardware reference 1679444SAndreas.Sandberg@ARM.com ipl = i; 1689444SAndreas.Sandberg@ARM.com summary |= (ULL(1) << i); 1699444SAndreas.Sandberg@ARM.com } 1702307SN/A } 1719444SAndreas.Sandberg@ARM.com } 1729444SAndreas.Sandberg@ARM.com 1739444SAndreas.Sandberg@ARM.com if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) { 1749444SAndreas.Sandberg@ARM.com newIpl = ipl; 1759444SAndreas.Sandberg@ARM.com newSummary = summary; 1769444SAndreas.Sandberg@ARM.com newInfoSet = true; 1779444SAndreas.Sandberg@ARM.com DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 1789444SAndreas.Sandberg@ARM.com tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary); 1799444SAndreas.Sandberg@ARM.com 1809444SAndreas.Sandberg@ARM.com return new InterruptFault; 1819444SAndreas.Sandberg@ARM.com } else { 1829444SAndreas.Sandberg@ARM.com return NoFault; 1832307SN/A } 1842307SN/A } 1852307SN/A 1862307SN/A void 1872307SN/A updateIntrInfo(ThreadContext *tc) 1882307SN/A { 1896221Snate@binkert.org assert(newInfoSet); 1902307SN/A tc->setMiscRegNoEffect(IPR_ISR, newSummary); 1912307SN/A tc->setMiscRegNoEffect(IPR_INTID, newIpl); 1922307SN/A newInfoSet = false; 1932307SN/A } 1942307SN/A}; 1952292SN/A 1966221Snate@binkert.org} // namespace AlphaISA 1972292SN/A 1982292SN/A#endif // __ARCH_ALPHA_INTERRUPT_HH__ 1992292SN/A 2002292SN/A