faults.hh revision 12110:c24ee249b8ba
12810SN/A/* 22810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Gabe Black 292810SN/A * Kevin Lim 302810SN/A */ 312810SN/A 322810SN/A#ifndef __ARCH_ALPHA_FAULTS_HH__ 332810SN/A#define __ARCH_ALPHA_FAULTS_HH__ 342810SN/A 352810SN/A#include "arch/alpha/pagetable.hh" 362810SN/A#include "mem/request.hh" 372810SN/A#include "sim/faults.hh" 382810SN/A 394626SN/A// The design of the "name" and "vect" functions is in sim/faults.hh 404626SN/A 415314SN/Anamespace AlphaISA { 422810SN/A 432810SN/Atypedef Addr FaultVect; 444626SN/A 454626SN/Aclass AlphaFault : public FaultBase 462810SN/A{ 472810SN/A protected: 482810SN/A virtual bool skipFaultingInstruction() {return false;} 493374SN/A virtual bool setRestartAddress() {return true;} 502810SN/A public: 515314SN/A virtual ~AlphaFault() {} 524626SN/A void invoke(ThreadContext * tc, const StaticInstPtr &inst = 534626SN/A StaticInst::nullStaticInstPtr); 542810SN/A virtual FaultVect vect() = 0; 554626SN/A virtual FaultStat & countStat() = 0; 564626SN/A}; 574626SN/A 585875Ssteve.reinhardt@amd.comclass MachineCheckFault : public AlphaFault 595875Ssteve.reinhardt@amd.com{ 605875Ssteve.reinhardt@amd.com private: 615875Ssteve.reinhardt@amd.com static FaultName _name; 625875Ssteve.reinhardt@amd.com static FaultVect _vect; 635875Ssteve.reinhardt@amd.com static FaultStat _count; 645875Ssteve.reinhardt@amd.com 654871SN/A public: 664871SN/A FaultName name() const {return _name;} 674666SN/A FaultVect vect() {return _vect;} 684626SN/A FaultStat & countStat() {return _count;} 695875Ssteve.reinhardt@amd.com}; 705318SN/A 715318SN/Aclass AlignmentFault : public AlphaFault 724626SN/A{ 735318SN/A private: 745875Ssteve.reinhardt@amd.com static FaultName _name; 754871SN/A static FaultVect _vect; 765875Ssteve.reinhardt@amd.com static FaultStat _count; 774626SN/A 784626SN/A public: 794626SN/A FaultName name() const {return _name;} 804903SN/A FaultVect vect() {return _vect;} 814903SN/A FaultStat & countStat() {return _count;} 824903SN/A bool isAlignmentFault() const {return true;} 835314SN/A}; 844903SN/A 854903SN/Aclass ResetFault : public AlphaFault 864903SN/A{ 874903SN/A private: 884903SN/A static FaultName _name; 894903SN/A static FaultVect _vect; 904903SN/A static FaultStat _count; 914903SN/A 925318SN/A public: 935875Ssteve.reinhardt@amd.com FaultName name() const {return _name;} 944903SN/A FaultVect vect() {return _vect;} 954908SN/A FaultStat & countStat() {return _count;} 964920SN/A}; 975314SN/A 985314SN/Aclass ArithmeticFault : public AlphaFault 994903SN/A{ 1004903SN/A private: 1012810SN/A static FaultName _name; 1022810SN/A static FaultVect _vect; 1032810SN/A static FaultStat _count; 1042810SN/A 1052810SN/A protected: 1062810SN/A bool skipFaultingInstruction() {return true;} 1072810SN/A 1084626SN/A public: 1094626SN/A FaultName name() const {return _name;} 1104626SN/A FaultVect vect() {return _vect;} 1114666SN/A FaultStat & countStat() {return _count;} 1124871SN/A void invoke(ThreadContext * tc, const StaticInstPtr &inst = 1134666SN/A StaticInst::nullStaticInstPtr); 1144666SN/A}; 1154666SN/A 1164666SN/Aclass InterruptFault : public AlphaFault 1174626SN/A{ 1182810SN/A private: 1194626SN/A static FaultName _name; 1204626SN/A static FaultVect _vect; 1214626SN/A static FaultStat _count; 1224626SN/A 1233374SN/A protected: 1242810SN/A bool setRestartAddress() {return false;} 1254626SN/A 1265730SSteve.Reinhardt@amd.com public: 1275730SSteve.Reinhardt@amd.com FaultName name() const {return _name;} 1284903SN/A FaultVect vect() {return _vect;} 1294626SN/A FaultStat & countStat() {return _count;} 1305314SN/A}; 1314665SN/A 1324626SN/Aclass DtbFault : public AlphaFault 1334626SN/A{ 1344626SN/A protected: 1354908SN/A VAddr vaddr; 1364908SN/A Request::Flags reqFlags; 1374665SN/A uint64_t flags; 1384670SN/A 1394665SN/A public: 1402810SN/A DtbFault(VAddr _vaddr, Request::Flags _reqFlags, uint64_t _flags) 1414626SN/A : vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags) 1422810SN/A { } 1432810SN/A FaultName name() const = 0; 1442810SN/A FaultVect vect() = 0; 1454668SN/A FaultStat & countStat() = 0; 1464668SN/A void invoke(ThreadContext * tc, const StaticInstPtr &inst = 1474668SN/A StaticInst::nullStaticInstPtr); 1484668SN/A}; 1494668SN/A 1502810SN/Aclass NDtbMissFault : public DtbFault 1512810SN/A{ 1522810SN/A private: 1532810SN/A static FaultName _name; 1542810SN/A static FaultVect _vect; 1554626SN/A static FaultStat _count; 1562810SN/A 1572810SN/A public: 1582810SN/A NDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) 1592810SN/A : DtbFault(vaddr, reqFlags, flags) 1602810SN/A { } 1612810SN/A FaultName name() const {return _name;} 1622810SN/A FaultVect vect() {return _vect;} 1633374SN/A FaultStat & countStat() {return _count;} 1644903SN/A void invoke(ThreadContext * tc, const StaticInstPtr &inst = 1652810SN/A StaticInst::nullStaticInstPtr); 1664903SN/A}; 1674665SN/A 1682810SN/Aclass PDtbMissFault : public DtbFault 1694626SN/A{ 1704626SN/A private: 1714626SN/A static FaultName _name; 1722810SN/A static FaultVect _vect; 1732810SN/A static FaultStat _count; 1743374SN/A 1752810SN/A public: 1762810SN/A PDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) 1773374SN/A : DtbFault(vaddr, reqFlags, flags) 1782982SN/A { } 1792810SN/A FaultName name() const {return _name;} 1804666SN/A FaultVect vect() {return _vect;} 1814666SN/A FaultStat & countStat() {return _count;} 1822810SN/A}; 1834908SN/A 1844908SN/Aclass DtbPageFault : public DtbFault 1855318SN/A{ 1865318SN/A private: 1872810SN/A static FaultName _name; 1882810SN/A static FaultVect _vect; 1892810SN/A static FaultStat _count; 1902810SN/A 1912810SN/A public: 1922810SN/A DtbPageFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) 1933374SN/A : DtbFault(vaddr, reqFlags, flags) 1942810SN/A { } 1952810SN/A FaultName name() const {return _name;} 1964666SN/A FaultVect vect() {return _vect;} 1974902SN/A FaultStat & countStat() {return _count;} 1982810SN/A}; 1992810SN/A 2002810SN/Aclass DtbAcvFault : public DtbFault 2012810SN/A{ 2022810SN/A private: 2032810SN/A static FaultName _name; 2042810SN/A static FaultVect _vect; 2052810SN/A static FaultStat _count; 2062810SN/A 2072810SN/A public: 2085730SSteve.Reinhardt@amd.com DtbAcvFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) 2092810SN/A : DtbFault(vaddr, reqFlags, flags) 2102810SN/A { } 2112810SN/A FaultName name() const {return _name;} 2122810SN/A FaultVect vect() {return _vect;} 2132810SN/A FaultStat & countStat() {return _count;} 2144903SN/A}; 2152810SN/A 2162810SN/Aclass DtbAlignmentFault : public DtbFault 2174899SN/A{ 2184899SN/A private: 2194899SN/A static FaultName _name; 2205730SSteve.Reinhardt@amd.com static FaultVect _vect; 2214899SN/A static FaultStat _count; 2224899SN/A 2232810SN/A public: 2242810SN/A DtbAlignmentFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) 2252810SN/A : DtbFault(vaddr, reqFlags, flags) 2265730SSteve.Reinhardt@amd.com { } 2275730SSteve.Reinhardt@amd.com FaultName name() const {return _name;} 2285730SSteve.Reinhardt@amd.com FaultVect vect() {return _vect;} 2295730SSteve.Reinhardt@amd.com FaultStat & countStat() {return _count;} 2305730SSteve.Reinhardt@amd.com}; 2312810SN/A 2322810SN/Aclass ItbFault : public AlphaFault 2332810SN/A{ 2342810SN/A protected: 2352810SN/A Addr pc; 2362810SN/A 2372810SN/A public: 2384903SN/A ItbFault(Addr _pc) : pc(_pc) { } 2392810SN/A FaultName name() const = 0; 2402810SN/A FaultVect vect() = 0; 2415730SSteve.Reinhardt@amd.com FaultStat & countStat() = 0; 2422810SN/A void invoke(ThreadContext * tc, const StaticInstPtr &inst = 2434630SN/A StaticInst::nullStaticInstPtr); 2444630SN/A}; 2454630SN/A 2465875Ssteve.reinhardt@amd.comclass ItbPageFault : public ItbFault 2472810SN/A{ 2482810SN/A private: 2494665SN/A static FaultName _name; 2504665SN/A static FaultVect _vect; 2514671SN/A static FaultStat _count; 2524668SN/A 2535314SN/A public: 2544920SN/A ItbPageFault(Addr pc) : ItbFault(pc) { } 2552810SN/A FaultName name() const {return _name;} 2565314SN/A FaultVect vect() {return _vect;} 2572810SN/A FaultStat & countStat() {return _count;} 2585314SN/A void invoke(ThreadContext * tc, const StaticInstPtr &inst = 2595314SN/A StaticInst::nullStaticInstPtr); 2605314SN/A}; 2612810SN/A 2622810SN/Aclass ItbAcvFault : public ItbFault 2632810SN/A{ 264 private: 265 static FaultName _name; 266 static FaultVect _vect; 267 static FaultStat _count; 268 269 public: 270 ItbAcvFault(Addr pc) : ItbFault(pc) { } 271 FaultName name() const {return _name;} 272 FaultVect vect() {return _vect;} 273 FaultStat & countStat() {return _count;} 274}; 275 276class UnimplementedOpcodeFault : public AlphaFault 277{ 278 private: 279 static FaultName _name; 280 static FaultVect _vect; 281 static FaultStat _count; 282 283 public: 284 FaultName name() const {return _name;} 285 FaultVect vect() {return _vect;} 286 FaultStat & countStat() {return _count;} 287}; 288 289class FloatEnableFault : public AlphaFault 290{ 291 private: 292 static FaultName _name; 293 static FaultVect _vect; 294 static FaultStat _count; 295 296 public: 297 FaultName name() const {return _name;} 298 FaultVect vect() {return _vect;} 299 FaultStat & countStat() {return _count;} 300}; 301 302class VectorEnableFault : public AlphaFault 303{ 304 private: 305 static FaultName _name; 306 static FaultVect _vect; 307 static FaultStat _count; 308 309 public: 310 FaultName name() const {return _name;} 311 FaultVect vect() {return _vect;} 312 FaultStat & countStat() {return _count;} 313}; 314 315class PalFault : public AlphaFault 316{ 317 private: 318 static FaultName _name; 319 static FaultVect _vect; 320 static FaultStat _count; 321 322 protected: 323 bool skipFaultingInstruction() {return true;} 324 325 public: 326 FaultName name() const {return _name;} 327 FaultVect vect() {return _vect;} 328 FaultStat & countStat() {return _count;} 329}; 330 331class IntegerOverflowFault : public AlphaFault 332{ 333 private: 334 static FaultName _name; 335 static FaultVect _vect; 336 static FaultStat _count; 337 338 public: 339 FaultName name() const {return _name;} 340 FaultVect vect() {return _vect;} 341 FaultStat & countStat() {return _count;} 342}; 343 344} // namespace AlphaISA 345 346#endif // __ARCH_ALPHA_FAULTS_HH__ 347