faults.cc revision 7678:f19b6a3a8cec 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include "arch/alpha/ev5.hh"
33#include "arch/alpha/faults.hh"
34#include "arch/alpha/tlb.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "base/trace.hh"
38
39#if !FULL_SYSTEM
40#include "sim/process.hh"
41#include "mem/page_table.hh"
42#endif
43
44namespace AlphaISA {
45
46FaultName MachineCheckFault::_name = "mchk";
47FaultVect MachineCheckFault::_vect = 0x0401;
48FaultStat MachineCheckFault::_count;
49
50FaultName AlignmentFault::_name = "unalign";
51FaultVect AlignmentFault::_vect = 0x0301;
52FaultStat AlignmentFault::_count;
53
54FaultName ResetFault::_name = "reset";
55FaultVect ResetFault::_vect = 0x0001;
56FaultStat ResetFault::_count;
57
58FaultName ArithmeticFault::_name = "arith";
59FaultVect ArithmeticFault::_vect = 0x0501;
60FaultStat ArithmeticFault::_count;
61
62FaultName InterruptFault::_name = "interrupt";
63FaultVect InterruptFault::_vect = 0x0101;
64FaultStat InterruptFault::_count;
65
66FaultName NDtbMissFault::_name = "dtb_miss_single";
67FaultVect NDtbMissFault::_vect = 0x0201;
68FaultStat NDtbMissFault::_count;
69
70FaultName PDtbMissFault::_name = "dtb_miss_double";
71FaultVect PDtbMissFault::_vect = 0x0281;
72FaultStat PDtbMissFault::_count;
73
74FaultName DtbPageFault::_name = "dfault";
75FaultVect DtbPageFault::_vect = 0x0381;
76FaultStat DtbPageFault::_count;
77
78FaultName DtbAcvFault::_name = "dfault";
79FaultVect DtbAcvFault::_vect = 0x0381;
80FaultStat DtbAcvFault::_count;
81
82FaultName DtbAlignmentFault::_name = "unalign";
83FaultVect DtbAlignmentFault::_vect = 0x0301;
84FaultStat DtbAlignmentFault::_count;
85
86FaultName ItbPageFault::_name = "itbmiss";
87FaultVect ItbPageFault::_vect = 0x0181;
88FaultStat ItbPageFault::_count;
89
90FaultName ItbAcvFault::_name = "iaccvio";
91FaultVect ItbAcvFault::_vect = 0x0081;
92FaultStat ItbAcvFault::_count;
93
94FaultName UnimplementedOpcodeFault::_name = "opdec";
95FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
96FaultStat UnimplementedOpcodeFault::_count;
97
98FaultName FloatEnableFault::_name = "fen";
99FaultVect FloatEnableFault::_vect = 0x0581;
100FaultStat FloatEnableFault::_count;
101
102FaultName PalFault::_name = "pal";
103FaultVect PalFault::_vect = 0x2001;
104FaultStat PalFault::_count;
105
106FaultName IntegerOverflowFault::_name = "intover";
107FaultVect IntegerOverflowFault::_vect = 0x0501;
108FaultStat IntegerOverflowFault::_count;
109
110#if FULL_SYSTEM
111
112void
113AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
114{
115    FaultBase::invoke(tc);
116    countStat()++;
117
118    // exception restart address
119    if (setRestartAddress() || !(tc->readPC() & 0x3))
120        tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC());
121
122    if (skipFaultingInstruction()) {
123        // traps...  skip faulting instruction.
124        tc->setMiscRegNoEffect(IPR_EXC_ADDR,
125                   tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
126    }
127
128    tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
129    tc->setNextPC(tc->readPC() + sizeof(MachInst));
130}
131
132void
133ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
134{
135    FaultBase::invoke(tc);
136    panic("Arithmetic traps are unimplemented!");
137}
138
139void
140DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
141{
142    // Set fault address and flags.  Even though we're modeling an
143    // EV5, we use the EV6 technique of not latching fault registers
144    // on VPTE loads (instead of locking the registers until IPR_VA is
145    // read, like the EV5).  The EV6 approach is cleaner and seems to
146    // work with EV5 PAL code, but not the other way around.
147    if (!tc->misspeculating() &&
148        reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
149        // set VA register with faulting address
150        tc->setMiscRegNoEffect(IPR_VA, vaddr);
151
152        // set MM_STAT register flags
153        MachInst machInst = inst->machInst;
154        tc->setMiscRegNoEffect(IPR_MM_STAT,
155            (((Opcode(machInst) & 0x3f) << 11) |
156             ((Ra(machInst) & 0x1f) << 6) |
157             (flags & 0x3f)));
158
159        // set VA_FORM register with faulting formatted address
160        tc->setMiscRegNoEffect(IPR_VA_FORM,
161            tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
162    }
163
164    AlphaFault::invoke(tc);
165}
166
167void
168ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
169{
170    if (!tc->misspeculating()) {
171        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
172        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
173            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
174    }
175
176    AlphaFault::invoke(tc);
177}
178
179#else
180
181void
182ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
183{
184    Process *p = tc->getProcessPtr();
185    TlbEntry entry;
186    bool success = p->pTable->lookup(pc, entry);
187    if (!success) {
188        panic("Tried to execute unmapped address %#x.\n", pc);
189    } else {
190        VAddr vaddr(pc);
191        tc->getITBPtr()->insert(vaddr.page(), entry);
192    }
193}
194
195void
196NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
197{
198    Process *p = tc->getProcessPtr();
199    TlbEntry entry;
200    bool success = p->pTable->lookup(vaddr, entry);
201    if (!success) {
202        p->checkAndAllocNextPage(vaddr);
203        success = p->pTable->lookup(vaddr, entry);
204    }
205    if (!success) {
206        panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
207    } else {
208        tc->getDTBPtr()->insert(vaddr.page(), entry);
209    }
210}
211
212#endif
213
214} // namespace AlphaISA
215
216