faults.cc revision 4183:3d19c1d46946 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include "arch/alpha/faults.hh"
33#include "cpu/thread_context.hh"
34#include "cpu/base.hh"
35#include "base/trace.hh"
36#if FULL_SYSTEM
37#include "arch/alpha/ev5.hh"
38#else
39#include "sim/process.hh"
40#include "mem/page_table.hh"
41#endif
42
43namespace AlphaISA
44{
45
46FaultName MachineCheckFault::_name = "mchk";
47FaultVect MachineCheckFault::_vect = 0x0401;
48FaultStat MachineCheckFault::_count;
49
50FaultName AlignmentFault::_name = "unalign";
51FaultVect AlignmentFault::_vect = 0x0301;
52FaultStat AlignmentFault::_count;
53
54FaultName ResetFault::_name = "reset";
55FaultVect ResetFault::_vect = 0x0001;
56FaultStat ResetFault::_count;
57
58FaultName ArithmeticFault::_name = "arith";
59FaultVect ArithmeticFault::_vect = 0x0501;
60FaultStat ArithmeticFault::_count;
61
62FaultName InterruptFault::_name = "interrupt";
63FaultVect InterruptFault::_vect = 0x0101;
64FaultStat InterruptFault::_count;
65
66FaultName NDtbMissFault::_name = "dtb_miss_single";
67FaultVect NDtbMissFault::_vect = 0x0201;
68FaultStat NDtbMissFault::_count;
69
70FaultName PDtbMissFault::_name = "dtb_miss_double";
71FaultVect PDtbMissFault::_vect = 0x0281;
72FaultStat PDtbMissFault::_count;
73
74FaultName DtbPageFault::_name = "dfault";
75FaultVect DtbPageFault::_vect = 0x0381;
76FaultStat DtbPageFault::_count;
77
78FaultName DtbAcvFault::_name = "dfault";
79FaultVect DtbAcvFault::_vect = 0x0381;
80FaultStat DtbAcvFault::_count;
81
82FaultName DtbAlignmentFault::_name = "unalign";
83FaultVect DtbAlignmentFault::_vect = 0x0301;
84FaultStat DtbAlignmentFault::_count;
85
86FaultName ItbMissFault::_name = "itbmiss";
87FaultVect ItbMissFault::_vect = 0x0181;
88FaultStat ItbMissFault::_count;
89
90FaultName ItbPageFault::_name = "itbmiss";
91FaultVect ItbPageFault::_vect = 0x0181;
92FaultStat ItbPageFault::_count;
93
94FaultName ItbAcvFault::_name = "iaccvio";
95FaultVect ItbAcvFault::_vect = 0x0081;
96FaultStat ItbAcvFault::_count;
97
98FaultName UnimplementedOpcodeFault::_name = "opdec";
99FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
100FaultStat UnimplementedOpcodeFault::_count;
101
102FaultName FloatEnableFault::_name = "fen";
103FaultVect FloatEnableFault::_vect = 0x0581;
104FaultStat FloatEnableFault::_count;
105
106FaultName PalFault::_name = "pal";
107FaultVect PalFault::_vect = 0x2001;
108FaultStat PalFault::_count;
109
110FaultName IntegerOverflowFault::_name = "intover";
111FaultVect IntegerOverflowFault::_vect = 0x0501;
112FaultStat IntegerOverflowFault::_count;
113
114#if FULL_SYSTEM
115
116void AlphaFault::invoke(ThreadContext * tc)
117{
118    FaultBase::invoke(tc);
119    countStat()++;
120
121    // exception restart address
122    if (setRestartAddress() || !(tc->readPC() & 0x3))
123        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
124
125    if (skipFaultingInstruction()) {
126        // traps...  skip faulting instruction.
127        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
128                   tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
129    }
130
131    tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
132    tc->setNextPC(tc->readPC() + sizeof(MachInst));
133}
134
135void ArithmeticFault::invoke(ThreadContext * tc)
136{
137    FaultBase::invoke(tc);
138    panic("Arithmetic traps are unimplemented!");
139}
140
141void DtbFault::invoke(ThreadContext * tc)
142{
143    // Set fault address and flags.  Even though we're modeling an
144    // EV5, we use the EV6 technique of not latching fault registers
145    // on VPTE loads (instead of locking the registers until IPR_VA is
146    // read, like the EV5).  The EV6 approach is cleaner and seems to
147    // work with EV5 PAL code, but not the other way around.
148    if (!tc->misspeculating()
149        && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
150        // set VA register with faulting address
151        tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
152
153        // set MM_STAT register flags
154        tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
155            (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
156             | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
157             | (flags & 0x3f)));
158
159        // set VA_FORM register with faulting formatted address
160        tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
161            tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
162    }
163
164    AlphaFault::invoke(tc);
165}
166
167void ItbFault::invoke(ThreadContext * tc)
168{
169    if (!tc->misspeculating()) {
170        tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
171        tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
172                       tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
173                       (AlphaISA::VAddr(pc).vpn() << 3));
174    }
175
176    AlphaFault::invoke(tc);
177}
178
179#endif
180
181} // namespace AlphaISA
182
183