faults.cc revision 4172:141705d83494 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include "arch/alpha/faults.hh"
33#include "cpu/thread_context.hh"
34#include "cpu/base.hh"
35#include "base/trace.hh"
36#if FULL_SYSTEM
37#include "arch/alpha/ev5.hh"
38#else
39#include "sim/process.hh"
40#include "mem/page_table.hh"
41#endif
42
43namespace AlphaISA
44{
45
46FaultName MachineCheckFault::_name = "mchk";
47FaultVect MachineCheckFault::_vect = 0x0401;
48FaultStat MachineCheckFault::_count;
49
50FaultName AlignmentFault::_name = "unalign";
51FaultVect AlignmentFault::_vect = 0x0301;
52FaultStat AlignmentFault::_count;
53
54FaultName ResetFault::_name = "reset";
55FaultVect ResetFault::_vect = 0x0001;
56FaultStat ResetFault::_count;
57
58FaultName ArithmeticFault::_name = "arith";
59FaultVect ArithmeticFault::_vect = 0x0501;
60FaultStat ArithmeticFault::_count;
61
62#if !FULL_SYSTEM
63FaultName PageTableFault::_name = "page_table_fault";
64FaultVect PageTableFault::_vect = 0x0000;
65FaultStat PageTableFault::_count;
66#endif
67
68FaultName InterruptFault::_name = "interrupt";
69FaultVect InterruptFault::_vect = 0x0101;
70FaultStat InterruptFault::_count;
71
72FaultName NDtbMissFault::_name = "dtb_miss_single";
73FaultVect NDtbMissFault::_vect = 0x0201;
74FaultStat NDtbMissFault::_count;
75
76FaultName PDtbMissFault::_name = "dtb_miss_double";
77FaultVect PDtbMissFault::_vect = 0x0281;
78FaultStat PDtbMissFault::_count;
79
80FaultName DtbPageFault::_name = "dfault";
81FaultVect DtbPageFault::_vect = 0x0381;
82FaultStat DtbPageFault::_count;
83
84FaultName DtbAcvFault::_name = "dfault";
85FaultVect DtbAcvFault::_vect = 0x0381;
86FaultStat DtbAcvFault::_count;
87
88FaultName DtbAlignmentFault::_name = "unalign";
89FaultVect DtbAlignmentFault::_vect = 0x0301;
90FaultStat DtbAlignmentFault::_count;
91
92FaultName ItbMissFault::_name = "itbmiss";
93FaultVect ItbMissFault::_vect = 0x0181;
94FaultStat ItbMissFault::_count;
95
96FaultName ItbPageFault::_name = "itbmiss";
97FaultVect ItbPageFault::_vect = 0x0181;
98FaultStat ItbPageFault::_count;
99
100FaultName ItbAcvFault::_name = "iaccvio";
101FaultVect ItbAcvFault::_vect = 0x0081;
102FaultStat ItbAcvFault::_count;
103
104FaultName UnimplementedOpcodeFault::_name = "opdec";
105FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
106FaultStat UnimplementedOpcodeFault::_count;
107
108FaultName FloatEnableFault::_name = "fen";
109FaultVect FloatEnableFault::_vect = 0x0581;
110FaultStat FloatEnableFault::_count;
111
112FaultName PalFault::_name = "pal";
113FaultVect PalFault::_vect = 0x2001;
114FaultStat PalFault::_count;
115
116FaultName IntegerOverflowFault::_name = "intover";
117FaultVect IntegerOverflowFault::_vect = 0x0501;
118FaultStat IntegerOverflowFault::_count;
119
120#if FULL_SYSTEM
121
122void AlphaFault::invoke(ThreadContext * tc)
123{
124    FaultBase::invoke(tc);
125    countStat()++;
126
127    // exception restart address
128    if (setRestartAddress() || !(tc->readPC() & 0x3))
129        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC());
130
131    if (skipFaultingInstruction()) {
132        // traps...  skip faulting instruction.
133        tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR,
134                   tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4);
135    }
136
137    tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect());
138    tc->setNextPC(tc->readPC() + sizeof(MachInst));
139}
140
141void ArithmeticFault::invoke(ThreadContext * tc)
142{
143    FaultBase::invoke(tc);
144    panic("Arithmetic traps are unimplemented!");
145}
146
147void DtbFault::invoke(ThreadContext * tc)
148{
149    // Set fault address and flags.  Even though we're modeling an
150    // EV5, we use the EV6 technique of not latching fault registers
151    // on VPTE loads (instead of locking the registers until IPR_VA is
152    // read, like the EV5).  The EV6 approach is cleaner and seems to
153    // work with EV5 PAL code, but not the other way around.
154    if (!tc->misspeculating()
155        && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
156        // set VA register with faulting address
157        tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr);
158
159        // set MM_STAT register flags
160        tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT,
161            (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
162             | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
163             | (flags & 0x3f)));
164
165        // set VA_FORM register with faulting formatted address
166        tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM,
167            tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
168    }
169
170    AlphaFault::invoke(tc);
171}
172
173void ItbFault::invoke(ThreadContext * tc)
174{
175    if (!tc->misspeculating()) {
176        tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc);
177        tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM,
178                       tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) |
179                       (AlphaISA::VAddr(pc).vpn() << 3));
180    }
181
182    AlphaFault::invoke(tc);
183}
184
185#else //!FULL_SYSTEM
186
187void PageTableFault::invoke(ThreadContext *tc)
188{
189    Process *p = tc->getProcessPtr();
190
191    // address is higher than the stack region or in the current stack region
192    if (vaddr > p->stack_base || vaddr > p->stack_min)
193        FaultBase::invoke(tc);
194
195    // We've accessed the next page
196    if (vaddr > p->stack_min - PageBytes) {
197        DPRINTF(Stack,
198                "Increasing stack %#x:%#x to %#x:%#x because of access to %#x",
199                p->stack_min, p->stack_base, p->stack_min - PageBytes,
200                p->stack_base, vaddr);
201        p->stack_min -= PageBytes;
202        if (p->stack_base - p->stack_min > 8*1024*1024)
203            fatal("Over max stack size for one thread\n");
204        p->pTable->allocate(p->stack_min, PageBytes);
205    } else {
206        warn("Page fault on address %#x\n", vaddr);
207        FaultBase::invoke(tc);
208    }
209}
210
211#endif
212
213} // namespace AlphaISA
214
215