faults.cc revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/alpha/faults.hh"
30#include "cpu/exec_context.hh"
31#include "cpu/base.hh"
32#include "base/trace.hh"
33#if FULL_SYSTEM
34#include "arch/alpha/ev5.hh"
35#endif
36
37namespace AlphaISA
38{
39
40FaultName MachineCheckFault::_name = "mchk";
41FaultVect MachineCheckFault::_vect = 0x0401;
42FaultStat MachineCheckFault::_count;
43
44FaultName AlignmentFault::_name = "unalign";
45FaultVect AlignmentFault::_vect = 0x0301;
46FaultStat AlignmentFault::_count;
47
48FaultName ResetFault::_name = "reset";
49FaultVect ResetFault::_vect = 0x0001;
50FaultStat ResetFault::_count;
51
52FaultName ArithmeticFault::_name = "arith";
53FaultVect ArithmeticFault::_vect = 0x0501;
54FaultStat ArithmeticFault::_count;
55
56FaultName InterruptFault::_name = "interrupt";
57FaultVect InterruptFault::_vect = 0x0101;
58FaultStat InterruptFault::_count;
59
60FaultName NDtbMissFault::_name = "dtb_miss_single";
61FaultVect NDtbMissFault::_vect = 0x0201;
62FaultStat NDtbMissFault::_count;
63
64FaultName PDtbMissFault::_name = "dtb_miss_double";
65FaultVect PDtbMissFault::_vect = 0x0281;
66FaultStat PDtbMissFault::_count;
67
68FaultName DtbPageFault::_name = "dfault";
69FaultVect DtbPageFault::_vect = 0x0381;
70FaultStat DtbPageFault::_count;
71
72FaultName DtbAcvFault::_name = "dfault";
73FaultVect DtbAcvFault::_vect = 0x0381;
74FaultStat DtbAcvFault::_count;
75
76FaultName DtbAlignmentFault::_name = "unalign";
77FaultVect DtbAlignmentFault::_vect = 0x0301;
78FaultStat DtbAlignmentFault::_count;
79
80FaultName ItbMissFault::_name = "itbmiss";
81FaultVect ItbMissFault::_vect = 0x0181;
82FaultStat ItbMissFault::_count;
83
84FaultName ItbPageFault::_name = "itbmiss";
85FaultVect ItbPageFault::_vect = 0x0181;
86FaultStat ItbPageFault::_count;
87
88FaultName ItbAcvFault::_name = "iaccvio";
89FaultVect ItbAcvFault::_vect = 0x0081;
90FaultStat ItbAcvFault::_count;
91
92FaultName UnimplementedOpcodeFault::_name = "opdec";
93FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
94FaultStat UnimplementedOpcodeFault::_count;
95
96FaultName FloatEnableFault::_name = "fen";
97FaultVect FloatEnableFault::_vect = 0x0581;
98FaultStat FloatEnableFault::_count;
99
100FaultName PalFault::_name = "pal";
101FaultVect PalFault::_vect = 0x2001;
102FaultStat PalFault::_count;
103
104FaultName IntegerOverflowFault::_name = "intover";
105FaultVect IntegerOverflowFault::_vect = 0x0501;
106FaultStat IntegerOverflowFault::_count;
107
108#if FULL_SYSTEM
109
110void AlphaFault::invoke(ExecContext * xc)
111{
112    FaultBase::invoke(xc);
113    countStat()++;
114
115    // exception restart address
116    if (setRestartAddress() || !xc->inPalMode())
117        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
118
119    if (skipFaultingInstruction()) {
120        // traps...  skip faulting instruction.
121        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
122                   xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
123    }
124
125    xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
126    xc->setNextPC(xc->readPC() + sizeof(MachInst));
127}
128
129void ArithmeticFault::invoke(ExecContext * xc)
130{
131    FaultBase::invoke(xc);
132    panic("Arithmetic traps are unimplemented!");
133}
134
135void DtbFault::invoke(ExecContext * xc)
136{
137    // Set fault address and flags.  Even though we're modeling an
138    // EV5, we use the EV6 technique of not latching fault registers
139    // on VPTE loads (instead of locking the registers until IPR_VA is
140    // read, like the EV5).  The EV6 approach is cleaner and seems to
141    // work with EV5 PAL code, but not the other way around.
142    if (!xc->misspeculating()
143        && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
144        // set VA register with faulting address
145        xc->setMiscReg(AlphaISA::IPR_VA, vaddr);
146
147        // set MM_STAT register flags
148        xc->setMiscReg(AlphaISA::IPR_MM_STAT,
149            (((EV5::Opcode(xc->getInst()) & 0x3f) << 11)
150             | ((EV5::Ra(xc->getInst()) & 0x1f) << 6)
151             | (flags & 0x3f)));
152
153        // set VA_FORM register with faulting formatted address
154        xc->setMiscReg(AlphaISA::IPR_VA_FORM,
155            xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
156    }
157
158    AlphaFault::invoke(xc);
159}
160
161void ItbFault::invoke(ExecContext * xc)
162{
163    if (!xc->misspeculating()) {
164        xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
165        xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
166                       xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
167                       (AlphaISA::VAddr(pc).vpn() << 3));
168    }
169
170    AlphaFault::invoke(xc);
171}
172
173#endif
174
175} // namespace AlphaISA
176
177