faults.cc revision 2201
111828Sjason@lowepower.com/* 211398SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 311398SN/A * All rights reserved. 411398SN/A * 511398SN/A * Redistribution and use in source and binary forms, with or without 611398SN/A * modification, are permitted provided that the following conditions are 711398SN/A * met: redistributions of source code must retain the above copyright 811398SN/A * notice, this list of conditions and the following disclaimer; 911398SN/A * redistributions in binary form must reproduce the above copyright 1011398SN/A * notice, this list of conditions and the following disclaimer in the 1111398SN/A * documentation and/or other materials provided with the distribution; 1211398SN/A * neither the name of the copyright holders nor the names of its 1311398SN/A * contributors may be used to endorse or promote products derived from 1411398SN/A * this software without specific prior written permission. 1511397SN/A * 1611397SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711397SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811397SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911397SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011397SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111397SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211397SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311397SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411397SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511397SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611397SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711397SN/A */ 2811397SN/A 2911397SN/A#include "arch/alpha/faults.hh" 3011397SN/A#include "cpu/exec_context.hh" 3111397SN/A#include "cpu/base.hh" 3211397SN/A#include "base/trace.hh" 3311397SN/A#include "kern/kernel_stats.hh" 3411397SN/A 3511397SN/Anamespace AlphaISA 3611397SN/A{ 3711397SN/A 3811397SN/AFaultVect AlphaMachineCheckFault::_vect = 0x0401; 3911397SN/AFaultStat AlphaMachineCheckFault::_stat; 4011397SN/A 4111397SN/AFaultVect AlphaAlignmentFault::_vect = 0x0301; 4211398SN/AFaultStat AlphaAlignmentFault::_stat; 4311397SN/A 448225SN/AFaultName ResetFault::_name = "reset"; 458225SN/AFaultVect ResetFault::_vect = 0x0001; 468225SN/AFaultStat ResetFault::_stat; 478225SN/A 488225SN/AFaultName ArithmeticFault::_name = "arith"; 498225SN/AFaultVect ArithmeticFault::_vect = 0x0501; 508225SN/AFaultStat ArithmeticFault::_stat; 518225SN/A 528225SN/AFaultName InterruptFault::_name = "interrupt"; 538225SN/AFaultVect InterruptFault::_vect = 0x0101; 548225SN/AFaultStat InterruptFault::_stat; 558225SN/A 568225SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 578225SN/AFaultVect NDtbMissFault::_vect = 0x0201; 588225SN/AFaultStat NDtbMissFault::_stat; 598225SN/A 608225SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 618225SN/AFaultVect PDtbMissFault::_vect = 0x0281; 628225SN/AFaultStat PDtbMissFault::_stat; 638225SN/A 648225SN/AFaultName DtbPageFault::_name = "dfault"; 658225SN/AFaultVect DtbPageFault::_vect = 0x0381; 668225SN/AFaultStat DtbPageFault::_stat; 678225SN/A 688225SN/AFaultName DtbAcvFault::_name = "dfault"; 698225SN/AFaultVect DtbAcvFault::_vect = 0x0381; 708225SN/AFaultStat DtbAcvFault::_stat; 718225SN/A 728225SN/AFaultName ItbMissFault::_name = "itbmiss"; 738225SN/AFaultVect ItbMissFault::_vect = 0x0181; 748225SN/AFaultStat ItbMissFault::_stat; 758225SN/A 768225SN/AFaultName ItbPageFault::_name = "itbmiss"; 778225SN/AFaultVect ItbPageFault::_vect = 0x0181; 788225SN/AFaultStat ItbPageFault::_stat; 798225SN/A 808225SN/AFaultName ItbAcvFault::_name = "iaccvio"; 818225SN/AFaultVect ItbAcvFault::_vect = 0x0081; 828225SN/AFaultStat ItbAcvFault::_stat; 838225SN/A 848225SN/AFaultName UnimplementedOpcodeFault::_name = "opdec"; 858225SN/AFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 868225SN/AFaultStat UnimplementedOpcodeFault::_stat; 878225SN/A 888225SN/AFaultName FloatEnableFault::_name = "fen"; 898225SN/AFaultVect FloatEnableFault::_vect = 0x0581; 908225SN/AFaultStat FloatEnableFault::_stat; 918225SN/A 928225SN/AFaultName PalFault::_name = "pal"; 9310674SN/AFaultVect PalFault::_vect = 0x2001; 9410674SN/AFaultStat PalFault::_stat; 9510674SN/A 9610674SN/AFaultName IntegerOverflowFault::_name = "intover"; 9710674SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 9810674SN/AFaultStat IntegerOverflowFault::_stat; 9910674SN/A 10010674SN/A#if FULL_SYSTEM 10110674SN/A 10210674SN/Avoid AlphaFault::invoke(ExecContext * xc) 10310674SN/A{ 10410674SN/A DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc); 10510674SN/A xc->cpu->recordEvent(csprintf("Fault %s", name())); 10610674SN/A 10710674SN/A assert(!xc->misspeculating()); 10810674SN/A xc->kernelStats->fault(this); 10910674SN/A 11010674SN/A // exception restart address 11110674SN/A if (setRestartAddress() || !xc->inPalMode()) 11210674SN/A xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc); 11310674SN/A 11410674SN/A if (skipFaultingInstruction()) { 11510674SN/A // traps... skip faulting instruction. 11610674SN/A xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, 11710674SN/A xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); 11810674SN/A } 11910674SN/A 12010674SN/A if (!xc->inPalMode()) 12110674SN/A AlphaISA::swap_palshadow(&(xc->regs), true); 12210674SN/A 12310674SN/A xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); 12410674SN/A xc->regs.npc = xc->regs.pc + sizeof(MachInst); 12510674SN/A} 12610674SN/A 12710674SN/Avoid ArithmeticFault::invoke(ExecContext * xc) 12810674SN/A{ 12910674SN/A DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc); 13010674SN/A xc->cpu->recordEvent(csprintf("Fault %s", name())); 13110674SN/A 13210674SN/A assert(!xc->misspeculating()); 13310674SN/A xc->kernelStats->fault(this); 13410674SN/A 13510674SN/A panic("Arithmetic traps are unimplemented!"); 13610674SN/A} 13710674SN/A 13810674SN/A 13910674SN/A/*void ArithmeticFault::invoke(ExecContext * xc) 14010674SN/A{ 14110674SN/A panic("Arithmetic traps are unimplemented!"); 14210674SN/A}*/ 14310674SN/A 14410674SN/A#endif 14510674SN/A 14610674SN/A} // namespace AlphaISA 14710674SN/A 14810674SN/A/*Fault * ListOfFaults[] = { 14910674SN/A (Fault *)&NoFault, 15010674SN/A (Fault *)&ResetFault, 1518225SN/A (Fault *)&MachineCheckFault, 1528225SN/A (Fault *)&ArithmeticFault, 1538225SN/A (Fault *)&InterruptFault, 1548225SN/A (Fault *)&NDtbMissFault, 1558225SN/A (Fault *)&PDtbMissFault, 1568225SN/A (Fault *)&AlignmentFault, 1578225SN/A (Fault *)&DtbPageFault, 1588225SN/A (Fault *)&DtbAcvFault, 15910674SN/A (Fault *)&ItbMissFault, 16010674SN/A (Fault *)&ItbPageFault, 16112009Sandreas.sandberg@arm.com (Fault *)&ItbAcvFault, 16212009Sandreas.sandberg@arm.com (Fault *)&UnimplementedOpcodeFault, 16310674SN/A (Fault *)&FloatEnableFault, 16410674SN/A (Fault *)&PalFault, 16510674SN/A (Fault *)&IntegerOverflowFault, 16610674SN/A }; 16710674SN/A 16810674SN/Aint NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/ 16910674SN/A