faults.cc revision 2198 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/alpha/faults.hh"
30#include "cpu/exec_context.hh"
31#include "cpu/base.hh"
32#include "base/trace.hh"
33#include "kern/kernel_stats.hh"
34
35namespace AlphaISA
36{
37
38FaultVect AlphaMachineCheckFault::_vect = 0x0401;
39FaultStat AlphaMachineCheckFault::_stat;
40
41FaultVect AlphaAlignmentFault::_vect = 0x0301;
42FaultStat AlphaAlignmentFault::_stat;
43
44FaultName ResetFault::_name = "reset";
45FaultVect ResetFault::_vect = 0x0001;
46FaultStat ResetFault::_stat;
47
48FaultName ArithmeticFault::_name = "arith";
49FaultVect ArithmeticFault::_vect = 0x0501;
50FaultStat ArithmeticFault::_stat;
51
52FaultName InterruptFault::_name = "interrupt";
53FaultVect InterruptFault::_vect = 0x0101;
54FaultStat InterruptFault::_stat;
55
56FaultName NDtbMissFault::_name = "dtb_miss_single";
57FaultVect NDtbMissFault::_vect = 0x0201;
58FaultStat NDtbMissFault::_stat;
59
60FaultName PDtbMissFault::_name = "dtb_miss_double";
61FaultVect PDtbMissFault::_vect = 0x0281;
62FaultStat PDtbMissFault::_stat;
63
64FaultName DtbPageFault::_name = "dfault";
65FaultVect DtbPageFault::_vect = 0x0381;
66FaultStat DtbPageFault::_stat;
67
68FaultName DtbAcvFault::_name = "dfault";
69FaultVect DtbAcvFault::_vect = 0x0381;
70FaultStat DtbAcvFault::_stat;
71
72FaultName ItbMissFault::_name = "itbmiss";
73FaultVect ItbMissFault::_vect = 0x0181;
74FaultStat ItbMissFault::_stat;
75
76FaultName ItbPageFault::_name = "itbmiss";
77FaultVect ItbPageFault::_vect = 0x0181;
78FaultStat ItbPageFault::_stat;
79
80FaultName ItbAcvFault::_name = "iaccvio";
81FaultVect ItbAcvFault::_vect = 0x0081;
82FaultStat ItbAcvFault::_stat;
83
84FaultName UnimplementedOpcodeFault::_name = "opdec";
85FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
86FaultStat UnimplementedOpcodeFault::_stat;
87
88FaultName FloatEnableFault::_name = "fen";
89FaultVect FloatEnableFault::_vect = 0x0581;
90FaultStat FloatEnableFault::_stat;
91
92FaultName PalFault::_name = "pal";
93FaultVect PalFault::_vect = 0x2001;
94FaultStat PalFault::_stat;
95
96FaultName IntegerOverflowFault::_name = "intover";
97FaultVect IntegerOverflowFault::_vect = 0x0501;
98FaultStat IntegerOverflowFault::_stat;
99
100#if FULL_SYSTEM
101
102void AlphaFault::invoke(ExecContext * xc)
103{
104    DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->regs.pc);
105    xc->cpu->recordEvent(csprintf("Fault %s", name()));
106
107    assert(!xc->misspeculating());
108    xc->kernelStats->fault(this);
109
110    if (isA<ArithmeticFault>())
111        panic("Arithmetic traps are unimplemented!");
112
113    // exception restart address
114    if (!isA<InterruptFault>() || !xc->inPalMode())
115        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
116
117    if (isA<PalFault>() || isA<ArithmeticFault>()) {
118        // traps...  skip faulting instruction.
119        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
120                   xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
121    }
122
123    if (!xc->inPalMode())
124        AlphaISA::swap_palshadow(&(xc->regs), true);
125
126    xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
127    xc->regs.npc = xc->regs.pc + sizeof(MachInst);
128}
129
130#endif
131
132} // namespace AlphaISA
133
134/*Fault * ListOfFaults[] = {
135        (Fault *)&NoFault,
136        (Fault *)&ResetFault,
137        (Fault *)&MachineCheckFault,
138        (Fault *)&ArithmeticFault,
139        (Fault *)&InterruptFault,
140        (Fault *)&NDtbMissFault,
141        (Fault *)&PDtbMissFault,
142        (Fault *)&AlignmentFault,
143        (Fault *)&DtbPageFault,
144        (Fault *)&DtbAcvFault,
145        (Fault *)&ItbMissFault,
146        (Fault *)&ItbPageFault,
147        (Fault *)&ItbAcvFault,
148        (Fault *)&UnimplementedOpcodeFault,
149        (Fault *)&FloatEnableFault,
150        (Fault *)&PalFault,
151        (Fault *)&IntegerOverflowFault,
152        };
153
154int NumFaults = sizeof(ListOfFaults) / sizeof(Fault *);*/
155