faults.cc revision 11793:ef606668d247 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Kevin Lim
30 */
31
32#include "arch/alpha/faults.hh"
33
34#include "arch/alpha/ev5.hh"
35#include "arch/alpha/tlb.hh"
36#include "base/trace.hh"
37#include "cpu/base.hh"
38#include "cpu/thread_context.hh"
39#include "mem/page_table.hh"
40#include "sim/full_system.hh"
41#include "sim/process.hh"
42
43namespace AlphaISA {
44
45FaultName MachineCheckFault::_name = "mchk";
46FaultVect MachineCheckFault::_vect = 0x0401;
47FaultStat MachineCheckFault::_count;
48
49FaultName AlignmentFault::_name = "unalign";
50FaultVect AlignmentFault::_vect = 0x0301;
51FaultStat AlignmentFault::_count;
52
53FaultName ResetFault::_name = "reset";
54FaultVect ResetFault::_vect = 0x0001;
55FaultStat ResetFault::_count;
56
57FaultName ArithmeticFault::_name = "arith";
58FaultVect ArithmeticFault::_vect = 0x0501;
59FaultStat ArithmeticFault::_count;
60
61FaultName InterruptFault::_name = "interrupt";
62FaultVect InterruptFault::_vect = 0x0101;
63FaultStat InterruptFault::_count;
64
65FaultName NDtbMissFault::_name = "dtb_miss_single";
66FaultVect NDtbMissFault::_vect = 0x0201;
67FaultStat NDtbMissFault::_count;
68
69FaultName PDtbMissFault::_name = "dtb_miss_double";
70FaultVect PDtbMissFault::_vect = 0x0281;
71FaultStat PDtbMissFault::_count;
72
73FaultName DtbPageFault::_name = "dtb_page_fault";
74FaultVect DtbPageFault::_vect = 0x0381;
75FaultStat DtbPageFault::_count;
76
77FaultName DtbAcvFault::_name = "dtb_acv_fault";
78FaultVect DtbAcvFault::_vect = 0x0381;
79FaultStat DtbAcvFault::_count;
80
81FaultName DtbAlignmentFault::_name = "unalign";
82FaultVect DtbAlignmentFault::_vect = 0x0301;
83FaultStat DtbAlignmentFault::_count;
84
85FaultName ItbPageFault::_name = "itbmiss";
86FaultVect ItbPageFault::_vect = 0x0181;
87FaultStat ItbPageFault::_count;
88
89FaultName ItbAcvFault::_name = "iaccvio";
90FaultVect ItbAcvFault::_vect = 0x0081;
91FaultStat ItbAcvFault::_count;
92
93FaultName UnimplementedOpcodeFault::_name = "opdec";
94FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
95FaultStat UnimplementedOpcodeFault::_count;
96
97FaultName FloatEnableFault::_name = "fen";
98FaultVect FloatEnableFault::_vect = 0x0581;
99FaultStat FloatEnableFault::_count;
100
101FaultName PalFault::_name = "pal";
102FaultVect PalFault::_vect = 0x2001;
103FaultStat PalFault::_count;
104
105FaultName IntegerOverflowFault::_name = "intover";
106FaultVect IntegerOverflowFault::_vect = 0x0501;
107FaultStat IntegerOverflowFault::_count;
108
109void
110AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
111{
112    FaultBase::invoke(tc);
113    if (!FullSystem)
114        return;
115    countStat()++;
116
117    PCState pc = tc->pcState();
118
119    // exception restart address
120    if (setRestartAddress() || !(pc.pc() & 0x3))
121        tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
122
123    if (skipFaultingInstruction()) {
124        // traps...  skip faulting instruction.
125        tc->setMiscRegNoEffect(IPR_EXC_ADDR,
126                   tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
127    }
128
129    pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
130    tc->pcState(pc);
131}
132
133void
134ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
135{
136    FaultBase::invoke(tc);
137    if (!FullSystem)
138        return;
139    panic("Arithmetic traps are unimplemented!");
140}
141
142void
143DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
144{
145    if (FullSystem) {
146        // Set fault address and flags.  Even though we're modeling an
147        // EV5, we use the EV6 technique of not latching fault registers
148        // on VPTE loads (instead of locking the registers until IPR_VA is
149        // read, like the EV5).  The EV6 approach is cleaner and seems to
150        // work with EV5 PAL code, but not the other way around.
151        if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
152            // set VA register with faulting address
153            tc->setMiscRegNoEffect(IPR_VA, vaddr);
154
155            // set MM_STAT register flags
156            MachInst machInst = inst->machInst;
157            tc->setMiscRegNoEffect(IPR_MM_STAT,
158                (((Opcode(machInst) & 0x3f) << 11) |
159                 ((Ra(machInst) & 0x1f) << 6) |
160                 (flags & 0x3f)));
161
162            // set VA_FORM register with faulting formatted address
163            tc->setMiscRegNoEffect(IPR_VA_FORM,
164                tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
165        }
166    }
167
168    AlphaFault::invoke(tc);
169}
170
171void
172ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
173{
174    if (FullSystem) {
175        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
176        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
177            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
178    }
179
180    AlphaFault::invoke(tc);
181}
182
183void
184ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
185{
186    if (FullSystem) {
187        ItbFault::invoke(tc);
188        return;
189    }
190
191    Process *p = tc->getProcessPtr();
192    TlbEntry entry;
193    bool success = p->pTable->lookup(pc, entry);
194    if (!success) {
195        panic("Tried to execute unmapped address %#x.\n", pc);
196    } else {
197        VAddr vaddr(pc);
198        tc->getITBPtr()->insert(vaddr.page(), entry);
199    }
200}
201
202void
203NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
204{
205    if (FullSystem) {
206        DtbFault::invoke(tc, inst);
207        return;
208    }
209
210    Process *p = tc->getProcessPtr();
211    TlbEntry entry;
212    bool success = p->pTable->lookup(vaddr, entry);
213    if (!success) {
214        if (p->fixupStackFault(vaddr))
215            success = p->pTable->lookup(vaddr, entry);
216    }
217    if (!success) {
218        panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
219    } else {
220        tc->getDTBPtr()->insert(vaddr.page(), entry);
221    }
222}
223
224} // namespace AlphaISA
225
226