faults.cc revision 5569
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510259SAndrew.Bardsley@arm.com * 1610259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * Authors: Gabe Black 2910259SAndrew.Bardsley@arm.com * Kevin Lim 3010259SAndrew.Bardsley@arm.com */ 3110259SAndrew.Bardsley@arm.com 3210259SAndrew.Bardsley@arm.com#include "arch/alpha/ev5.hh" 3310259SAndrew.Bardsley@arm.com#include "arch/alpha/faults.hh" 3410259SAndrew.Bardsley@arm.com#include "arch/alpha/tlb.hh" 3510259SAndrew.Bardsley@arm.com#include "cpu/thread_context.hh" 3610259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 3710259SAndrew.Bardsley@arm.com#include "base/trace.hh" 3810259SAndrew.Bardsley@arm.com#if !FULL_SYSTEM 3910259SAndrew.Bardsley@arm.com#include "sim/process.hh" 4010259SAndrew.Bardsley@arm.com#include "mem/page_table.hh" 4110259SAndrew.Bardsley@arm.com#endif 4210259SAndrew.Bardsley@arm.com 4310259SAndrew.Bardsley@arm.comnamespace AlphaISA { 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.comFaultName MachineCheckFault::_name = "mchk"; 4610259SAndrew.Bardsley@arm.comFaultVect MachineCheckFault::_vect = 0x0401; 4710259SAndrew.Bardsley@arm.comFaultStat MachineCheckFault::_count; 4810259SAndrew.Bardsley@arm.com 4910259SAndrew.Bardsley@arm.comFaultName AlignmentFault::_name = "unalign"; 5010259SAndrew.Bardsley@arm.comFaultVect AlignmentFault::_vect = 0x0301; 5110259SAndrew.Bardsley@arm.comFaultStat AlignmentFault::_count; 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.comFaultName ResetFault::_name = "reset"; 5410259SAndrew.Bardsley@arm.comFaultVect ResetFault::_vect = 0x0001; 5510259SAndrew.Bardsley@arm.comFaultStat ResetFault::_count; 5610259SAndrew.Bardsley@arm.com 5710259SAndrew.Bardsley@arm.comFaultName ArithmeticFault::_name = "arith"; 5810259SAndrew.Bardsley@arm.comFaultVect ArithmeticFault::_vect = 0x0501; 5910259SAndrew.Bardsley@arm.comFaultStat ArithmeticFault::_count; 6010259SAndrew.Bardsley@arm.com 6110259SAndrew.Bardsley@arm.comFaultName InterruptFault::_name = "interrupt"; 6210259SAndrew.Bardsley@arm.comFaultVect InterruptFault::_vect = 0x0101; 6310259SAndrew.Bardsley@arm.comFaultStat InterruptFault::_count; 6410259SAndrew.Bardsley@arm.com 6510259SAndrew.Bardsley@arm.comFaultName NDtbMissFault::_name = "dtb_miss_single"; 6610259SAndrew.Bardsley@arm.comFaultVect NDtbMissFault::_vect = 0x0201; 6710259SAndrew.Bardsley@arm.comFaultStat NDtbMissFault::_count; 6810259SAndrew.Bardsley@arm.com 6910259SAndrew.Bardsley@arm.comFaultName PDtbMissFault::_name = "dtb_miss_double"; 7010259SAndrew.Bardsley@arm.comFaultVect PDtbMissFault::_vect = 0x0281; 7110259SAndrew.Bardsley@arm.comFaultStat PDtbMissFault::_count; 7210259SAndrew.Bardsley@arm.com 7310259SAndrew.Bardsley@arm.comFaultName DtbPageFault::_name = "dfault"; 7410259SAndrew.Bardsley@arm.comFaultVect DtbPageFault::_vect = 0x0381; 7510259SAndrew.Bardsley@arm.comFaultStat DtbPageFault::_count; 7610259SAndrew.Bardsley@arm.com 7710259SAndrew.Bardsley@arm.comFaultName DtbAcvFault::_name = "dfault"; 7810259SAndrew.Bardsley@arm.comFaultVect DtbAcvFault::_vect = 0x0381; 7910259SAndrew.Bardsley@arm.comFaultStat DtbAcvFault::_count; 8010259SAndrew.Bardsley@arm.com 8110259SAndrew.Bardsley@arm.comFaultName DtbAlignmentFault::_name = "unalign"; 8210259SAndrew.Bardsley@arm.comFaultVect DtbAlignmentFault::_vect = 0x0301; 8310259SAndrew.Bardsley@arm.comFaultStat DtbAlignmentFault::_count; 8410259SAndrew.Bardsley@arm.com 8510259SAndrew.Bardsley@arm.comFaultName ItbPageFault::_name = "itbmiss"; 8610259SAndrew.Bardsley@arm.comFaultVect ItbPageFault::_vect = 0x0181; 8710259SAndrew.Bardsley@arm.comFaultStat ItbPageFault::_count; 8810259SAndrew.Bardsley@arm.com 8910259SAndrew.Bardsley@arm.comFaultName ItbAcvFault::_name = "iaccvio"; 9010259SAndrew.Bardsley@arm.comFaultVect ItbAcvFault::_vect = 0x0081; 9110259SAndrew.Bardsley@arm.comFaultStat ItbAcvFault::_count; 9210259SAndrew.Bardsley@arm.com 9310259SAndrew.Bardsley@arm.comFaultName UnimplementedOpcodeFault::_name = "opdec"; 9410259SAndrew.Bardsley@arm.comFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 9510259SAndrew.Bardsley@arm.comFaultStat UnimplementedOpcodeFault::_count; 9610259SAndrew.Bardsley@arm.com 9710259SAndrew.Bardsley@arm.comFaultName FloatEnableFault::_name = "fen"; 9810259SAndrew.Bardsley@arm.comFaultVect FloatEnableFault::_vect = 0x0581; 9910259SAndrew.Bardsley@arm.comFaultStat FloatEnableFault::_count; 10010259SAndrew.Bardsley@arm.com 10110259SAndrew.Bardsley@arm.comFaultName PalFault::_name = "pal"; 10210259SAndrew.Bardsley@arm.comFaultVect PalFault::_vect = 0x2001; 10310259SAndrew.Bardsley@arm.comFaultStat PalFault::_count; 10410259SAndrew.Bardsley@arm.com 10510259SAndrew.Bardsley@arm.comFaultName IntegerOverflowFault::_name = "intover"; 10610259SAndrew.Bardsley@arm.comFaultVect IntegerOverflowFault::_vect = 0x0501; 10710259SAndrew.Bardsley@arm.comFaultStat IntegerOverflowFault::_count; 10810259SAndrew.Bardsley@arm.com 10910259SAndrew.Bardsley@arm.com#if FULL_SYSTEM 11010259SAndrew.Bardsley@arm.com 11110259SAndrew.Bardsley@arm.comvoid 11210259SAndrew.Bardsley@arm.comAlphaFault::invoke(ThreadContext *tc) 11310259SAndrew.Bardsley@arm.com{ 11410259SAndrew.Bardsley@arm.com FaultBase::invoke(tc); 11510259SAndrew.Bardsley@arm.com countStat()++; 11610259SAndrew.Bardsley@arm.com 11710259SAndrew.Bardsley@arm.com // exception restart address 11810259SAndrew.Bardsley@arm.com if (setRestartAddress() || !(tc->readPC() & 0x3)) 11910259SAndrew.Bardsley@arm.com tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC()); 12010259SAndrew.Bardsley@arm.com 12110259SAndrew.Bardsley@arm.com if (skipFaultingInstruction()) { 12210259SAndrew.Bardsley@arm.com // traps... skip faulting instruction. 12310259SAndrew.Bardsley@arm.com tc->setMiscRegNoEffect(IPR_EXC_ADDR, 12410259SAndrew.Bardsley@arm.com tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4); 12510259SAndrew.Bardsley@arm.com } 12610259SAndrew.Bardsley@arm.com 12710259SAndrew.Bardsley@arm.com tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect()); 12810259SAndrew.Bardsley@arm.com tc->setNextPC(tc->readPC() + sizeof(MachInst)); 12910259SAndrew.Bardsley@arm.com} 13010259SAndrew.Bardsley@arm.com 13110259SAndrew.Bardsley@arm.comvoid 13210259SAndrew.Bardsley@arm.comArithmeticFault::invoke(ThreadContext *tc) 13310259SAndrew.Bardsley@arm.com{ 13410259SAndrew.Bardsley@arm.com FaultBase::invoke(tc); 13510259SAndrew.Bardsley@arm.com panic("Arithmetic traps are unimplemented!"); 13610259SAndrew.Bardsley@arm.com} 13710259SAndrew.Bardsley@arm.com 13810259SAndrew.Bardsley@arm.comvoid 13910259SAndrew.Bardsley@arm.comDtbFault::invoke(ThreadContext *tc) 14010259SAndrew.Bardsley@arm.com{ 14110259SAndrew.Bardsley@arm.com // Set fault address and flags. Even though we're modeling an 14210259SAndrew.Bardsley@arm.com // EV5, we use the EV6 technique of not latching fault registers 14310259SAndrew.Bardsley@arm.com // on VPTE loads (instead of locking the registers until IPR_VA is 14410259SAndrew.Bardsley@arm.com // read, like the EV5). The EV6 approach is cleaner and seems to 14510259SAndrew.Bardsley@arm.com // work with EV5 PAL code, but not the other way around. 14610259SAndrew.Bardsley@arm.com if (!tc->misspeculating() && 14710259SAndrew.Bardsley@arm.com !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { 14810259SAndrew.Bardsley@arm.com // set VA register with faulting address 14910259SAndrew.Bardsley@arm.com tc->setMiscRegNoEffect(IPR_VA, vaddr); 15010259SAndrew.Bardsley@arm.com 15110259SAndrew.Bardsley@arm.com // set MM_STAT register flags 15210259SAndrew.Bardsley@arm.com tc->setMiscRegNoEffect(IPR_MM_STAT, 15310259SAndrew.Bardsley@arm.com (((Opcode(tc->getInst()) & 0x3f) << 11) | 15410259SAndrew.Bardsley@arm.com ((Ra(tc->getInst()) & 0x1f) << 6) | 15510259SAndrew.Bardsley@arm.com (flags & 0x3f))); 15610259SAndrew.Bardsley@arm.com 15710259SAndrew.Bardsley@arm.com // set VA_FORM register with faulting formatted address 15810259SAndrew.Bardsley@arm.com tc->setMiscRegNoEffect(IPR_VA_FORM, 15910259SAndrew.Bardsley@arm.com tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3)); 16010259SAndrew.Bardsley@arm.com } 16110259SAndrew.Bardsley@arm.com 16210259SAndrew.Bardsley@arm.com AlphaFault::invoke(tc); 16310259SAndrew.Bardsley@arm.com} 16410259SAndrew.Bardsley@arm.com 16510259SAndrew.Bardsley@arm.comvoid 16610259SAndrew.Bardsley@arm.comItbFault::invoke(ThreadContext *tc) 16710259SAndrew.Bardsley@arm.com{ 16810259SAndrew.Bardsley@arm.com if (!tc->misspeculating()) { 16910259SAndrew.Bardsley@arm.com tc->setMiscRegNoEffect(IPR_ITB_TAG, pc); 17010259SAndrew.Bardsley@arm.com tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM, 17110259SAndrew.Bardsley@arm.com tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3)); 17210259SAndrew.Bardsley@arm.com } 17310259SAndrew.Bardsley@arm.com 17410259SAndrew.Bardsley@arm.com AlphaFault::invoke(tc); 17510259SAndrew.Bardsley@arm.com} 17610259SAndrew.Bardsley@arm.com 17710259SAndrew.Bardsley@arm.com#else 17810259SAndrew.Bardsley@arm.com 17910259SAndrew.Bardsley@arm.comvoid 18010259SAndrew.Bardsley@arm.comItbPageFault::invoke(ThreadContext *tc) 18110259SAndrew.Bardsley@arm.com{ 18210259SAndrew.Bardsley@arm.com Process *p = tc->getProcessPtr(); 18310259SAndrew.Bardsley@arm.com TlbEntry entry; 18410259SAndrew.Bardsley@arm.com bool success = p->pTable->lookup(pc, entry); 18510259SAndrew.Bardsley@arm.com if (!success) { 18610259SAndrew.Bardsley@arm.com panic("Tried to execute unmapped address %#x.\n", pc); 18710259SAndrew.Bardsley@arm.com } else { 18810259SAndrew.Bardsley@arm.com VAddr vaddr(pc); 18910259SAndrew.Bardsley@arm.com tc->getITBPtr()->insert(vaddr.page(), entry); 19010259SAndrew.Bardsley@arm.com } 19110259SAndrew.Bardsley@arm.com} 19210259SAndrew.Bardsley@arm.com 19310259SAndrew.Bardsley@arm.comvoid 19410259SAndrew.Bardsley@arm.comNDtbMissFault::invoke(ThreadContext *tc) 19510259SAndrew.Bardsley@arm.com{ 19610259SAndrew.Bardsley@arm.com Process *p = tc->getProcessPtr(); 19710259SAndrew.Bardsley@arm.com TlbEntry entry; 19810259SAndrew.Bardsley@arm.com bool success = p->pTable->lookup(vaddr, entry); 19910259SAndrew.Bardsley@arm.com if (!success) { 20010259SAndrew.Bardsley@arm.com p->checkAndAllocNextPage(vaddr); 20110259SAndrew.Bardsley@arm.com success = p->pTable->lookup(vaddr, entry); 20210259SAndrew.Bardsley@arm.com } 20310259SAndrew.Bardsley@arm.com if (!success) { 20410259SAndrew.Bardsley@arm.com panic("Tried to access unmapped address %#x.\n", (Addr)vaddr); 20510259SAndrew.Bardsley@arm.com } else { 20610259SAndrew.Bardsley@arm.com tc->getDTBPtr()->insert(vaddr.page(), entry); 20710259SAndrew.Bardsley@arm.com } 20810259SAndrew.Bardsley@arm.com} 20910259SAndrew.Bardsley@arm.com 21010259SAndrew.Bardsley@arm.com#endif 21110259SAndrew.Bardsley@arm.com 21210259SAndrew.Bardsley@arm.com} // namespace AlphaISA 21310259SAndrew.Bardsley@arm.com 21410259SAndrew.Bardsley@arm.com