faults.cc revision 5568
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Kevin Lim 302SN/A */ 312SN/A 324997Sgblack@eecs.umich.edu#include "arch/alpha/ev5.hh" 331110SN/A#include "arch/alpha/faults.hh" 344997Sgblack@eecs.umich.edu#include "arch/alpha/tlb.hh" 352680Sktlim@umich.edu#include "cpu/thread_context.hh" 362196SN/A#include "cpu/base.hh" 372196SN/A#include "base/trace.hh" 384997Sgblack@eecs.umich.edu#if !FULL_SYSTEM 392800Ssaidi@eecs.umich.edu#include "sim/process.hh" 402800Ssaidi@eecs.umich.edu#include "mem/page_table.hh" 412289SN/A#endif 422SN/A 432167SN/Anamespace AlphaISA 442167SN/A{ 452167SN/A 462203SN/AFaultName MachineCheckFault::_name = "mchk"; 472203SN/AFaultVect MachineCheckFault::_vect = 0x0401; 482222SN/AFaultStat MachineCheckFault::_count; 492166SN/A 502203SN/AFaultName AlignmentFault::_name = "unalign"; 512203SN/AFaultVect AlignmentFault::_vect = 0x0301; 522222SN/AFaultStat AlignmentFault::_count; 532166SN/A 542147SN/AFaultName ResetFault::_name = "reset"; 552147SN/AFaultVect ResetFault::_vect = 0x0001; 562222SN/AFaultStat ResetFault::_count; 572147SN/A 582147SN/AFaultName ArithmeticFault::_name = "arith"; 592147SN/AFaultVect ArithmeticFault::_vect = 0x0501; 602222SN/AFaultStat ArithmeticFault::_count; 612147SN/A 622147SN/AFaultName InterruptFault::_name = "interrupt"; 632147SN/AFaultVect InterruptFault::_vect = 0x0101; 642222SN/AFaultStat InterruptFault::_count; 652147SN/A 662147SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 672147SN/AFaultVect NDtbMissFault::_vect = 0x0201; 682222SN/AFaultStat NDtbMissFault::_count; 692147SN/A 702147SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 712147SN/AFaultVect PDtbMissFault::_vect = 0x0281; 722222SN/AFaultStat PDtbMissFault::_count; 732147SN/A 742147SN/AFaultName DtbPageFault::_name = "dfault"; 752147SN/AFaultVect DtbPageFault::_vect = 0x0381; 762222SN/AFaultStat DtbPageFault::_count; 772147SN/A 782147SN/AFaultName DtbAcvFault::_name = "dfault"; 792147SN/AFaultVect DtbAcvFault::_vect = 0x0381; 802222SN/AFaultStat DtbAcvFault::_count; 812147SN/A 822289SN/AFaultName DtbAlignmentFault::_name = "unalign"; 832289SN/AFaultVect DtbAlignmentFault::_vect = 0x0301; 842289SN/AFaultStat DtbAlignmentFault::_count; 852289SN/A 862147SN/AFaultName ItbPageFault::_name = "itbmiss"; 872147SN/AFaultVect ItbPageFault::_vect = 0x0181; 882222SN/AFaultStat ItbPageFault::_count; 892147SN/A 902147SN/AFaultName ItbAcvFault::_name = "iaccvio"; 912147SN/AFaultVect ItbAcvFault::_vect = 0x0081; 922222SN/AFaultStat ItbAcvFault::_count; 932147SN/A 942147SN/AFaultName UnimplementedOpcodeFault::_name = "opdec"; 952147SN/AFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 962222SN/AFaultStat UnimplementedOpcodeFault::_count; 972147SN/A 982147SN/AFaultName FloatEnableFault::_name = "fen"; 992147SN/AFaultVect FloatEnableFault::_vect = 0x0581; 1002222SN/AFaultStat FloatEnableFault::_count; 1012147SN/A 1022147SN/AFaultName PalFault::_name = "pal"; 1032147SN/AFaultVect PalFault::_vect = 0x2001; 1042222SN/AFaultStat PalFault::_count; 1052147SN/A 1062147SN/AFaultName IntegerOverflowFault::_name = "intover"; 1072147SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 1082222SN/AFaultStat IntegerOverflowFault::_count; 1092147SN/A 1102174SN/A#if FULL_SYSTEM 1112174SN/A 1122680Sktlim@umich.eduvoid AlphaFault::invoke(ThreadContext * tc) 1132174SN/A{ 1142680Sktlim@umich.edu FaultBase::invoke(tc); 1152222SN/A countStat()++; 1162174SN/A 1172196SN/A // exception restart address 1183521Sgblack@eecs.umich.edu if (setRestartAddress() || !(tc->readPC() & 0x3)) 1195568Snate@binkert.org tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC()); 1202196SN/A 1212201SN/A if (skipFaultingInstruction()) { 1222196SN/A // traps... skip faulting instruction. 1235568Snate@binkert.org tc->setMiscRegNoEffect(IPR_EXC_ADDR, 1245568Snate@binkert.org tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4); 1252196SN/A } 1262196SN/A 1275568Snate@binkert.org tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect()); 1282680Sktlim@umich.edu tc->setNextPC(tc->readPC() + sizeof(MachInst)); 1292174SN/A} 1302174SN/A 1312680Sktlim@umich.eduvoid ArithmeticFault::invoke(ThreadContext * tc) 1322201SN/A{ 1332680Sktlim@umich.edu FaultBase::invoke(tc); 1342201SN/A panic("Arithmetic traps are unimplemented!"); 1352201SN/A} 1362201SN/A 1372680Sktlim@umich.eduvoid DtbFault::invoke(ThreadContext * tc) 1382289SN/A{ 1392289SN/A // Set fault address and flags. Even though we're modeling an 1402289SN/A // EV5, we use the EV6 technique of not latching fault registers 1412289SN/A // on VPTE loads (instead of locking the registers until IPR_VA is 1422289SN/A // read, like the EV5). The EV6 approach is cleaner and seems to 1432289SN/A // work with EV5 PAL code, but not the other way around. 1442680Sktlim@umich.edu if (!tc->misspeculating() 1452289SN/A && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { 1462289SN/A // set VA register with faulting address 1475568Snate@binkert.org tc->setMiscRegNoEffect(IPR_VA, vaddr); 1482289SN/A 1492289SN/A // set MM_STAT register flags 1505568Snate@binkert.org tc->setMiscRegNoEffect(IPR_MM_STAT, 1515568Snate@binkert.org (((Opcode(tc->getInst()) & 0x3f) << 11) 1525568Snate@binkert.org | ((Ra(tc->getInst()) & 0x1f) << 6) 1532289SN/A | (flags & 0x3f))); 1542289SN/A 1552289SN/A // set VA_FORM register with faulting formatted address 1565568Snate@binkert.org tc->setMiscRegNoEffect(IPR_VA_FORM, 1575568Snate@binkert.org tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3)); 1582289SN/A } 1592289SN/A 1602680Sktlim@umich.edu AlphaFault::invoke(tc); 1612289SN/A} 1622289SN/A 1632680Sktlim@umich.eduvoid ItbFault::invoke(ThreadContext * tc) 1642289SN/A{ 1652680Sktlim@umich.edu if (!tc->misspeculating()) { 1665568Snate@binkert.org tc->setMiscRegNoEffect(IPR_ITB_TAG, pc); 1675568Snate@binkert.org tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM, 1685568Snate@binkert.org tc->readMiscRegNoEffect(IPR_IVPTBR) | 1695568Snate@binkert.org (VAddr(pc).vpn() << 3)); 1702289SN/A } 1712289SN/A 1722680Sktlim@umich.edu AlphaFault::invoke(tc); 1732289SN/A} 1742289SN/A 1754997Sgblack@eecs.umich.edu#else 1764997Sgblack@eecs.umich.edu 1774997Sgblack@eecs.umich.eduvoid ItbPageFault::invoke(ThreadContext * tc) 1784997Sgblack@eecs.umich.edu{ 1794997Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 1805184Sgblack@eecs.umich.edu TlbEntry entry; 1815184Sgblack@eecs.umich.edu bool success = p->pTable->lookup(pc, entry); 1824997Sgblack@eecs.umich.edu if(!success) { 1834997Sgblack@eecs.umich.edu panic("Tried to execute unmapped address %#x.\n", pc); 1844997Sgblack@eecs.umich.edu } else { 1854997Sgblack@eecs.umich.edu VAddr vaddr(pc); 1865004Sgblack@eecs.umich.edu tc->getITBPtr()->insert(vaddr.page(), entry); 1874997Sgblack@eecs.umich.edu } 1884997Sgblack@eecs.umich.edu} 1894997Sgblack@eecs.umich.edu 1904997Sgblack@eecs.umich.eduvoid NDtbMissFault::invoke(ThreadContext * tc) 1914997Sgblack@eecs.umich.edu{ 1924997Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 1935184Sgblack@eecs.umich.edu TlbEntry entry; 1945184Sgblack@eecs.umich.edu bool success = p->pTable->lookup(vaddr, entry); 1954997Sgblack@eecs.umich.edu if(!success) { 1964997Sgblack@eecs.umich.edu p->checkAndAllocNextPage(vaddr); 1975184Sgblack@eecs.umich.edu success = p->pTable->lookup(vaddr, entry); 1984997Sgblack@eecs.umich.edu } 1994997Sgblack@eecs.umich.edu if(!success) { 2004997Sgblack@eecs.umich.edu panic("Tried to access unmapped address %#x.\n", (Addr)vaddr); 2014997Sgblack@eecs.umich.edu } else { 2025004Sgblack@eecs.umich.edu tc->getDTBPtr()->insert(vaddr.page(), entry); 2034997Sgblack@eecs.umich.edu } 2044997Sgblack@eecs.umich.edu} 2054997Sgblack@eecs.umich.edu 2062174SN/A#endif 2072174SN/A 2082167SN/A} // namespace AlphaISA 2092167SN/A 210