faults.cc revision 2800
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Kevin Lim 302SN/A */ 312SN/A 321110SN/A#include "arch/alpha/faults.hh" 332680Sktlim@umich.edu#include "cpu/thread_context.hh" 342196SN/A#include "cpu/base.hh" 352196SN/A#include "base/trace.hh" 362289SN/A#if FULL_SYSTEM 372289SN/A#include "arch/alpha/ev5.hh" 382800Ssaidi@eecs.umich.edu#else 392800Ssaidi@eecs.umich.edu#include "sim/process.hh" 402800Ssaidi@eecs.umich.edu#include "mem/page_table.hh" 412289SN/A#endif 422SN/A 432167SN/Anamespace AlphaISA 442167SN/A{ 452167SN/A 462203SN/AFaultName MachineCheckFault::_name = "mchk"; 472203SN/AFaultVect MachineCheckFault::_vect = 0x0401; 482222SN/AFaultStat MachineCheckFault::_count; 492166SN/A 502203SN/AFaultName AlignmentFault::_name = "unalign"; 512203SN/AFaultVect AlignmentFault::_vect = 0x0301; 522222SN/AFaultStat AlignmentFault::_count; 532166SN/A 542147SN/AFaultName ResetFault::_name = "reset"; 552147SN/AFaultVect ResetFault::_vect = 0x0001; 562222SN/AFaultStat ResetFault::_count; 572147SN/A 582147SN/AFaultName ArithmeticFault::_name = "arith"; 592147SN/AFaultVect ArithmeticFault::_vect = 0x0501; 602222SN/AFaultStat ArithmeticFault::_count; 612147SN/A 622800Ssaidi@eecs.umich.edu#if !FULL_SYSTEM 632800Ssaidi@eecs.umich.eduFaultName PageTableFault::_name = "page_table_fault"; 642800Ssaidi@eecs.umich.eduFaultVect PageTableFault::_vect = 0x0000; 652800Ssaidi@eecs.umich.eduFaultStat PageTableFault::_count; 662800Ssaidi@eecs.umich.edu#endif 672800Ssaidi@eecs.umich.edu 682147SN/AFaultName InterruptFault::_name = "interrupt"; 692147SN/AFaultVect InterruptFault::_vect = 0x0101; 702222SN/AFaultStat InterruptFault::_count; 712147SN/A 722147SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 732147SN/AFaultVect NDtbMissFault::_vect = 0x0201; 742222SN/AFaultStat NDtbMissFault::_count; 752147SN/A 762147SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 772147SN/AFaultVect PDtbMissFault::_vect = 0x0281; 782222SN/AFaultStat PDtbMissFault::_count; 792147SN/A 802147SN/AFaultName DtbPageFault::_name = "dfault"; 812147SN/AFaultVect DtbPageFault::_vect = 0x0381; 822222SN/AFaultStat DtbPageFault::_count; 832147SN/A 842147SN/AFaultName DtbAcvFault::_name = "dfault"; 852147SN/AFaultVect DtbAcvFault::_vect = 0x0381; 862222SN/AFaultStat DtbAcvFault::_count; 872147SN/A 882289SN/AFaultName DtbAlignmentFault::_name = "unalign"; 892289SN/AFaultVect DtbAlignmentFault::_vect = 0x0301; 902289SN/AFaultStat DtbAlignmentFault::_count; 912289SN/A 922147SN/AFaultName ItbMissFault::_name = "itbmiss"; 932147SN/AFaultVect ItbMissFault::_vect = 0x0181; 942222SN/AFaultStat ItbMissFault::_count; 952147SN/A 962147SN/AFaultName ItbPageFault::_name = "itbmiss"; 972147SN/AFaultVect ItbPageFault::_vect = 0x0181; 982222SN/AFaultStat ItbPageFault::_count; 992147SN/A 1002147SN/AFaultName ItbAcvFault::_name = "iaccvio"; 1012147SN/AFaultVect ItbAcvFault::_vect = 0x0081; 1022222SN/AFaultStat ItbAcvFault::_count; 1032147SN/A 1042147SN/AFaultName UnimplementedOpcodeFault::_name = "opdec"; 1052147SN/AFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 1062222SN/AFaultStat UnimplementedOpcodeFault::_count; 1072147SN/A 1082147SN/AFaultName FloatEnableFault::_name = "fen"; 1092147SN/AFaultVect FloatEnableFault::_vect = 0x0581; 1102222SN/AFaultStat FloatEnableFault::_count; 1112147SN/A 1122147SN/AFaultName PalFault::_name = "pal"; 1132147SN/AFaultVect PalFault::_vect = 0x2001; 1142222SN/AFaultStat PalFault::_count; 1152147SN/A 1162147SN/AFaultName IntegerOverflowFault::_name = "intover"; 1172147SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 1182222SN/AFaultStat IntegerOverflowFault::_count; 1192147SN/A 1202174SN/A#if FULL_SYSTEM 1212174SN/A 1222680Sktlim@umich.eduvoid AlphaFault::invoke(ThreadContext * tc) 1232174SN/A{ 1242680Sktlim@umich.edu FaultBase::invoke(tc); 1252222SN/A countStat()++; 1262174SN/A 1272196SN/A // exception restart address 1282680Sktlim@umich.edu if (setRestartAddress() || !tc->inPalMode()) 1292680Sktlim@umich.edu tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC()); 1302196SN/A 1312201SN/A if (skipFaultingInstruction()) { 1322196SN/A // traps... skip faulting instruction. 1332680Sktlim@umich.edu tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, 1342680Sktlim@umich.edu tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); 1352196SN/A } 1362196SN/A 1372680Sktlim@umich.edu tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect()); 1382680Sktlim@umich.edu tc->setNextPC(tc->readPC() + sizeof(MachInst)); 1392174SN/A} 1402174SN/A 1412680Sktlim@umich.eduvoid ArithmeticFault::invoke(ThreadContext * tc) 1422201SN/A{ 1432680Sktlim@umich.edu FaultBase::invoke(tc); 1442201SN/A panic("Arithmetic traps are unimplemented!"); 1452201SN/A} 1462201SN/A 1472680Sktlim@umich.eduvoid DtbFault::invoke(ThreadContext * tc) 1482289SN/A{ 1492289SN/A // Set fault address and flags. Even though we're modeling an 1502289SN/A // EV5, we use the EV6 technique of not latching fault registers 1512289SN/A // on VPTE loads (instead of locking the registers until IPR_VA is 1522289SN/A // read, like the EV5). The EV6 approach is cleaner and seems to 1532289SN/A // work with EV5 PAL code, but not the other way around. 1542680Sktlim@umich.edu if (!tc->misspeculating() 1552289SN/A && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { 1562289SN/A // set VA register with faulting address 1572680Sktlim@umich.edu tc->setMiscReg(AlphaISA::IPR_VA, vaddr); 1582289SN/A 1592289SN/A // set MM_STAT register flags 1602680Sktlim@umich.edu tc->setMiscReg(AlphaISA::IPR_MM_STAT, 1612680Sktlim@umich.edu (((EV5::Opcode(tc->getInst()) & 0x3f) << 11) 1622680Sktlim@umich.edu | ((EV5::Ra(tc->getInst()) & 0x1f) << 6) 1632289SN/A | (flags & 0x3f))); 1642289SN/A 1652289SN/A // set VA_FORM register with faulting formatted address 1662680Sktlim@umich.edu tc->setMiscReg(AlphaISA::IPR_VA_FORM, 1672680Sktlim@umich.edu tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); 1682289SN/A } 1692289SN/A 1702680Sktlim@umich.edu AlphaFault::invoke(tc); 1712289SN/A} 1722289SN/A 1732680Sktlim@umich.eduvoid ItbFault::invoke(ThreadContext * tc) 1742289SN/A{ 1752680Sktlim@umich.edu if (!tc->misspeculating()) { 1762680Sktlim@umich.edu tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); 1772680Sktlim@umich.edu tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, 1782680Sktlim@umich.edu tc->readMiscReg(AlphaISA::IPR_IVPTBR) | 1792289SN/A (AlphaISA::VAddr(pc).vpn() << 3)); 1802289SN/A } 1812289SN/A 1822680Sktlim@umich.edu AlphaFault::invoke(tc); 1832289SN/A} 1842289SN/A 1852800Ssaidi@eecs.umich.edu#else //!FULL_SYSTEM 1862800Ssaidi@eecs.umich.edu 1872800Ssaidi@eecs.umich.eduvoid PageTableFault::invoke(ThreadContext *tc) 1882800Ssaidi@eecs.umich.edu{ 1892800Ssaidi@eecs.umich.edu Process *p = tc->getProcessPtr(); 1902800Ssaidi@eecs.umich.edu 1912800Ssaidi@eecs.umich.edu // address is higher than the stack region or in the current stack region 1922800Ssaidi@eecs.umich.edu if (vaddr > p->stack_base || vaddr > p->stack_min) 1932800Ssaidi@eecs.umich.edu FaultBase::invoke(tc); 1942800Ssaidi@eecs.umich.edu 1952800Ssaidi@eecs.umich.edu // We've accessed the next page 1962800Ssaidi@eecs.umich.edu if (vaddr > p->stack_min - PageBytes) { 1972800Ssaidi@eecs.umich.edu p->stack_min -= PageBytes; 1982800Ssaidi@eecs.umich.edu if (p->stack_base - p->stack_min > 8*1024*1024) 1992800Ssaidi@eecs.umich.edu fatal("Over max stack size for one thread\n"); 2002800Ssaidi@eecs.umich.edu p->pTable->allocate(p->stack_min, PageBytes); 2012800Ssaidi@eecs.umich.edu warn("Increasing stack size by one page."); 2022800Ssaidi@eecs.umich.edu } else { 2032800Ssaidi@eecs.umich.edu FaultBase::invoke(tc); 2042800Ssaidi@eecs.umich.edu } 2052800Ssaidi@eecs.umich.edu} 2062800Ssaidi@eecs.umich.edu 2072174SN/A#endif 2082174SN/A 2092167SN/A} // namespace AlphaISA 2102167SN/A 211