faults.cc revision 2665
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Kevin Lim 302SN/A */ 312SN/A 321110SN/A#include "arch/alpha/faults.hh" 332174SN/A#include "cpu/exec_context.hh" 342196SN/A#include "cpu/base.hh" 352196SN/A#include "base/trace.hh" 362289SN/A#if FULL_SYSTEM 372289SN/A#include "arch/alpha/ev5.hh" 382289SN/A#endif 392SN/A 402167SN/Anamespace AlphaISA 412167SN/A{ 422167SN/A 432203SN/AFaultName MachineCheckFault::_name = "mchk"; 442203SN/AFaultVect MachineCheckFault::_vect = 0x0401; 452222SN/AFaultStat MachineCheckFault::_count; 462166SN/A 472203SN/AFaultName AlignmentFault::_name = "unalign"; 482203SN/AFaultVect AlignmentFault::_vect = 0x0301; 492222SN/AFaultStat AlignmentFault::_count; 502166SN/A 512147SN/AFaultName ResetFault::_name = "reset"; 522147SN/AFaultVect ResetFault::_vect = 0x0001; 532222SN/AFaultStat ResetFault::_count; 542147SN/A 552147SN/AFaultName ArithmeticFault::_name = "arith"; 562147SN/AFaultVect ArithmeticFault::_vect = 0x0501; 572222SN/AFaultStat ArithmeticFault::_count; 582147SN/A 592147SN/AFaultName InterruptFault::_name = "interrupt"; 602147SN/AFaultVect InterruptFault::_vect = 0x0101; 612222SN/AFaultStat InterruptFault::_count; 622147SN/A 632147SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 642147SN/AFaultVect NDtbMissFault::_vect = 0x0201; 652222SN/AFaultStat NDtbMissFault::_count; 662147SN/A 672147SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 682147SN/AFaultVect PDtbMissFault::_vect = 0x0281; 692222SN/AFaultStat PDtbMissFault::_count; 702147SN/A 712147SN/AFaultName DtbPageFault::_name = "dfault"; 722147SN/AFaultVect DtbPageFault::_vect = 0x0381; 732222SN/AFaultStat DtbPageFault::_count; 742147SN/A 752147SN/AFaultName DtbAcvFault::_name = "dfault"; 762147SN/AFaultVect DtbAcvFault::_vect = 0x0381; 772222SN/AFaultStat DtbAcvFault::_count; 782147SN/A 792289SN/AFaultName DtbAlignmentFault::_name = "unalign"; 802289SN/AFaultVect DtbAlignmentFault::_vect = 0x0301; 812289SN/AFaultStat DtbAlignmentFault::_count; 822289SN/A 832147SN/AFaultName ItbMissFault::_name = "itbmiss"; 842147SN/AFaultVect ItbMissFault::_vect = 0x0181; 852222SN/AFaultStat ItbMissFault::_count; 862147SN/A 872147SN/AFaultName ItbPageFault::_name = "itbmiss"; 882147SN/AFaultVect ItbPageFault::_vect = 0x0181; 892222SN/AFaultStat ItbPageFault::_count; 902147SN/A 912147SN/AFaultName ItbAcvFault::_name = "iaccvio"; 922147SN/AFaultVect ItbAcvFault::_vect = 0x0081; 932222SN/AFaultStat ItbAcvFault::_count; 942147SN/A 952147SN/AFaultName UnimplementedOpcodeFault::_name = "opdec"; 962147SN/AFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 972222SN/AFaultStat UnimplementedOpcodeFault::_count; 982147SN/A 992147SN/AFaultName FloatEnableFault::_name = "fen"; 1002147SN/AFaultVect FloatEnableFault::_vect = 0x0581; 1012222SN/AFaultStat FloatEnableFault::_count; 1022147SN/A 1032147SN/AFaultName PalFault::_name = "pal"; 1042147SN/AFaultVect PalFault::_vect = 0x2001; 1052222SN/AFaultStat PalFault::_count; 1062147SN/A 1072147SN/AFaultName IntegerOverflowFault::_name = "intover"; 1082147SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 1092222SN/AFaultStat IntegerOverflowFault::_count; 1102147SN/A 1112174SN/A#if FULL_SYSTEM 1122174SN/A 1132198SN/Avoid AlphaFault::invoke(ExecContext * xc) 1142174SN/A{ 1152222SN/A FaultBase::invoke(xc); 1162222SN/A countStat()++; 1172174SN/A 1182196SN/A // exception restart address 1192201SN/A if (setRestartAddress() || !xc->inPalMode()) 1202235SN/A xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC()); 1212196SN/A 1222201SN/A if (skipFaultingInstruction()) { 1232196SN/A // traps... skip faulting instruction. 1242196SN/A xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, 1252196SN/A xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); 1262196SN/A } 1272196SN/A 1282235SN/A xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect()); 1292235SN/A xc->setNextPC(xc->readPC() + sizeof(MachInst)); 1302174SN/A} 1312174SN/A 1322201SN/Avoid ArithmeticFault::invoke(ExecContext * xc) 1332201SN/A{ 1342222SN/A FaultBase::invoke(xc); 1352201SN/A panic("Arithmetic traps are unimplemented!"); 1362201SN/A} 1372201SN/A 1382289SN/Avoid DtbFault::invoke(ExecContext * xc) 1392289SN/A{ 1402289SN/A // Set fault address and flags. Even though we're modeling an 1412289SN/A // EV5, we use the EV6 technique of not latching fault registers 1422289SN/A // on VPTE loads (instead of locking the registers until IPR_VA is 1432289SN/A // read, like the EV5). The EV6 approach is cleaner and seems to 1442289SN/A // work with EV5 PAL code, but not the other way around. 1452289SN/A if (!xc->misspeculating() 1462289SN/A && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { 1472289SN/A // set VA register with faulting address 1482289SN/A xc->setMiscReg(AlphaISA::IPR_VA, vaddr); 1492289SN/A 1502289SN/A // set MM_STAT register flags 1512289SN/A xc->setMiscReg(AlphaISA::IPR_MM_STAT, 1522289SN/A (((EV5::Opcode(xc->getInst()) & 0x3f) << 11) 1532289SN/A | ((EV5::Ra(xc->getInst()) & 0x1f) << 6) 1542289SN/A | (flags & 0x3f))); 1552289SN/A 1562289SN/A // set VA_FORM register with faulting formatted address 1572289SN/A xc->setMiscReg(AlphaISA::IPR_VA_FORM, 1582289SN/A xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); 1592289SN/A } 1602289SN/A 1612289SN/A AlphaFault::invoke(xc); 1622289SN/A} 1632289SN/A 1642289SN/Avoid ItbFault::invoke(ExecContext * xc) 1652289SN/A{ 1662289SN/A if (!xc->misspeculating()) { 1672289SN/A xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); 1682289SN/A xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, 1692289SN/A xc->readMiscReg(AlphaISA::IPR_IVPTBR) | 1702289SN/A (AlphaISA::VAddr(pc).vpn() << 3)); 1712289SN/A } 1722289SN/A 1732289SN/A AlphaFault::invoke(xc); 1742289SN/A} 1752289SN/A 1762174SN/A#endif 1772174SN/A 1782167SN/A} // namespace AlphaISA 1792167SN/A 180