faults.cc revision 2222
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#include "arch/alpha/faults.hh" 302SN/A#include "cpu/exec_context.hh" 312SN/A#include "cpu/base.hh" 322SN/A#include "base/trace.hh" 332SN/A 342SN/Anamespace AlphaISA 351984SN/A{ 36857SN/A 371984SN/AFaultName MachineCheckFault::_name = "mchk"; 382650Ssaidi@eecs.umich.eduFaultVect MachineCheckFault::_vect = 0x0401; 392SN/AFaultStat MachineCheckFault::_count; 401984SN/A 412SN/AFaultName AlignmentFault::_name = "unalign"; 422SN/AFaultVect AlignmentFault::_vect = 0x0301; 431912SN/AFaultStat AlignmentFault::_count; 442130SN/A 45857SN/AFaultName ResetFault::_name = "reset"; 462SN/AFaultVect ResetFault::_vect = 0x0001; 471912SN/AFaultStat ResetFault::_count; 482SN/A 492SN/AFaultName ArithmeticFault::_name = "arith"; 502SN/AFaultVect ArithmeticFault::_vect = 0x0501; 511912SN/AFaultStat ArithmeticFault::_count; 521912SN/A 531912SN/AFaultName InterruptFault::_name = "interrupt"; 541912SN/AFaultVect InterruptFault::_vect = 0x0101; 551912SN/AFaultStat InterruptFault::_count; 561912SN/A 571912SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 581912SN/AFaultVect NDtbMissFault::_vect = 0x0201; 591912SN/AFaultStat NDtbMissFault::_count; 601912SN/A 611912SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 621912SN/AFaultVect PDtbMissFault::_vect = 0x0281; 631912SN/AFaultStat PDtbMissFault::_count; 641912SN/A 652SN/AFaultName DtbPageFault::_name = "dfault"; 662SN/AFaultVect DtbPageFault::_vect = 0x0381; 672SN/AFaultStat DtbPageFault::_count; 682SN/A 692SN/AFaultName DtbAcvFault::_name = "dfault"; 701984SN/AFaultVect DtbAcvFault::_vect = 0x0381; 712SN/AFaultStat DtbAcvFault::_count; 722SN/A 732SN/AFaultName ItbMissFault::_name = "itbmiss"; 741912SN/AFaultVect ItbMissFault::_vect = 0x0181; 751912SN/AFaultStat ItbMissFault::_count; 761912SN/A 771912SN/AFaultName ItbPageFault::_name = "itbmiss"; 781984SN/AFaultVect ItbPageFault::_vect = 0x0181; 791984SN/AFaultStat ItbPageFault::_count; 801984SN/A 811984SN/AFaultName ItbAcvFault::_name = "iaccvio"; 821984SN/AFaultVect ItbAcvFault::_vect = 0x0081; 831912SN/AFaultStat ItbAcvFault::_count; 841912SN/A 851912SN/AFaultName UnimplementedOpcodeFault::_name = "opdec"; 861912SN/AFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 871912SN/AFaultStat UnimplementedOpcodeFault::_count; 881912SN/A 891912SN/AFaultName FloatEnableFault::_name = "fen"; 901912SN/AFaultVect FloatEnableFault::_vect = 0x0581; 911912SN/AFaultStat FloatEnableFault::_count; 921912SN/A 931912SN/AFaultName PalFault::_name = "pal"; 941912SN/AFaultVect PalFault::_vect = 0x2001; 951912SN/AFaultStat PalFault::_count; 961912SN/A 971912SN/AFaultName IntegerOverflowFault::_name = "intover"; 981912SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 991912SN/AFaultStat IntegerOverflowFault::_count; 1001912SN/A 1011912SN/A#if FULL_SYSTEM 1021912SN/A 1031912SN/Avoid AlphaFault::invoke(ExecContext * xc) 1041912SN/A{ 1051158SN/A FaultBase::invoke(xc); 1061158SN/A countStat()++; 1072982Sstever@eecs.umich.edu 1082982Sstever@eecs.umich.edu // exception restart address 1092982Sstever@eecs.umich.edu if (setRestartAddress() || !xc->inPalMode()) 1102982Sstever@eecs.umich.edu xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc); 1112982Sstever@eecs.umich.edu 1121158SN/A if (skipFaultingInstruction()) { 1131912SN/A // traps... skip faulting instruction. 1141912SN/A xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, 1151912SN/A xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); 1161912SN/A } 1171912SN/A 1181912SN/A if (!xc->inPalMode()) 1191912SN/A AlphaISA::swap_palshadow(&(xc->regs), true); 1201912SN/A 1211912SN/A xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); 1221912SN/A xc->regs.npc = xc->regs.pc + sizeof(MachInst); 1231912SN/A} 1241912SN/A 1251912SN/Avoid ArithmeticFault::invoke(ExecContext * xc) 1261912SN/A{ 1271158SN/A FaultBase::invoke(xc); 1281158SN/A panic("Arithmetic traps are unimplemented!"); 1292982Sstever@eecs.umich.edu} 1301912SN/A 1311912SN/A#endif 1321158SN/A 1331912SN/A} // namespace AlphaISA 1341912SN/A 1351912SN/A