ev5.hh revision 2665
11758SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 31758SN/A * All rights reserved. 41758SN/A * 51758SN/A * Redistribution and use in source and binary forms, with or without 61758SN/A * modification, are permitted provided that the following conditions are 71758SN/A * met: redistributions of source code must retain the above copyright 81758SN/A * notice, this list of conditions and the following disclaimer; 91758SN/A * redistributions in binary form must reproduce the above copyright 101758SN/A * notice, this list of conditions and the following disclaimer in the 111758SN/A * documentation and/or other materials provided with the distribution; 121758SN/A * neither the name of the copyright holders nor the names of its 131758SN/A * contributors may be used to endorse or promote products derived from 141758SN/A * this software without specific prior written permission. 151758SN/A * 161758SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171758SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181758SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191758SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201758SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211758SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221758SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231758SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241758SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251758SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261758SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302665Ssaidi@eecs.umich.edu * Ali Saidi 311758SN/A */ 322SN/A 331147SN/A#ifndef __ARCH_ALPHA_EV5_HH__ 341147SN/A#define __ARCH_ALPHA_EV5_HH__ 352SN/A 361858SN/A#include "config/alpha_tlaser.hh" 372107SN/A#include "arch/alpha/isa_traits.hh" 381858SN/A 391147SN/Anamespace EV5 { 40924SN/A 412107SN/A//It seems like a safe assumption EV5 only applies to alpha 422107SN/Ausing namespace AlphaISA; 432107SN/A 441858SN/A#if ALPHA_TLASER 451147SN/Aconst uint64_t AsnMask = ULL(0x7f); 46924SN/A#else 471147SN/Aconst uint64_t AsnMask = ULL(0xff); 48924SN/A#endif 49924SN/A 501147SN/Aconst int VAddrImplBits = 43; 511147SN/Aconst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 521147SN/Aconst Addr VAddrUnImplMask = ~VAddrImplMask; 531147SN/Ainline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 541147SN/Ainline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 551147SN/Ainline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 561147SN/Ainline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 571147SN/Ainline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 58924SN/A 591858SN/A#if ALPHA_TLASER 601147SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 611147SN/Aconst int PAddrImplBits = 40; 62924SN/A#else 631147SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 641147SN/Aconst int PAddrImplBits = 44; // for Tsunami 65924SN/A#endif 661147SN/Aconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 671147SN/Aconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 681147SN/Aconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 691147SN/Aconst Addr PAddrUncachedBit43 = ULL(0x80000000000); 701147SN/Aconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 711805SN/Ainline Addr Phys2K0Seg(Addr addr) 721805SN/A{ 731858SN/A#if !ALPHA_TLASER 741805SN/A if (addr & PAddrUncachedBit43) { 751805SN/A addr &= PAddrUncachedMask; 761805SN/A addr |= PAddrUncachedBit40; 771805SN/A } 781805SN/A#endif 791805SN/A return addr | AlphaISA::K0SegBase; 801805SN/A} 81924SN/A 821147SN/Ainline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 831147SN/Ainline Addr DTB_PTE_PPN(uint64_t reg) 841147SN/A{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 851147SN/Ainline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 861147SN/Ainline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 871147SN/Ainline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 881147SN/Ainline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 891147SN/Ainline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 901147SN/Ainline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 912SN/A 921147SN/Ainline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 931147SN/Ainline Addr ITB_PTE_PPN(uint64_t reg) 941147SN/A{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 951147SN/Ainline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 961147SN/Ainline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 971147SN/Ainline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 981147SN/Ainline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 991147SN/Ainline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 1002SN/A 1011147SN/Ainline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 1022SN/A 1031147SN/Ainline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 1041147SN/Ainline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 1051147SN/Ainline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 1062SN/A 1071147SN/Ainline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 1081147SN/Ainline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1091147SN/Ainline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1102SN/A 1111147SN/Aconst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 1121147SN/Aconst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 1131147SN/Aconst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 1141147SN/Aconst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 1151147SN/Aconst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 1161147SN/Aconst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 1171147SN/Ainline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 1181147SN/Ainline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 1192SN/A 1201147SN/Aconst Addr PalBase = 0x4000; 1211147SN/Aconst Addr PalMax = 0x10000; 1222SN/A 1231147SN/A/* namespace EV5 */ } 1242SN/A 1251147SN/A#endif // __ARCH_ALPHA_EV5_HH__ 126