ev5.hh revision 1858
12124SN/A/* 22124SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32124SN/A * All rights reserved. 42124SN/A * 52022SN/A * Redistribution and use in source and binary forms, with or without 62124SN/A * modification, are permitted provided that the following conditions are 72124SN/A * met: redistributions of source code must retain the above copyright 82124SN/A * notice, this list of conditions and the following disclaimer; 92124SN/A * redistributions in binary form must reproduce the above copyright 102124SN/A * notice, this list of conditions and the following disclaimer in the 112124SN/A * documentation and/or other materials provided with the distribution; 122124SN/A * neither the name of the copyright holders nor the names of its 132124SN/A * contributors may be used to endorse or promote products derived from 142124SN/A * this software without specific prior written permission. 152124SN/A * 162022SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172124SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182124SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192124SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202124SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212124SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222124SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232124SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242124SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252124SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262124SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272124SN/A */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __ARCH_ALPHA_EV5_HH__ 302665Ssaidi@eecs.umich.edu#define __ARCH_ALPHA_EV5_HH__ 312022SN/A 322649Ssaidi@eecs.umich.edu#include "config/alpha_tlaser.hh" 332649Ssaidi@eecs.umich.edu 342706Sksewell@umich.edunamespace EV5 { 352649Ssaidi@eecs.umich.edu 362649Ssaidi@eecs.umich.edu#if ALPHA_TLASER 372022SN/Aconst uint64_t AsnMask = ULL(0x7f); 382124SN/A#else 392124SN/Aconst uint64_t AsnMask = ULL(0xff); 402124SN/A#endif 412124SN/A 422124SN/Aconst int VAddrImplBits = 43; 432124SN/Aconst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 442124SN/Aconst Addr VAddrUnImplMask = ~VAddrImplMask; 452124SN/Ainline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 462124SN/Ainline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 472124SN/Ainline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 482124SN/Ainline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 492124SN/Ainline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 502124SN/A 512239SN/A#if ALPHA_TLASER 522124SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 532124SN/Aconst int PAddrImplBits = 40; 542124SN/A#else 552124SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 562124SN/Aconst int PAddrImplBits = 44; // for Tsunami 572124SN/A#endif 582124SN/Aconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 592124SN/Aconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 602124SN/Aconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 612742Sksewell@umich.educonst Addr PAddrUncachedBit43 = ULL(0x80000000000); 622022SN/Aconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 632124SN/Ainline Addr Phys2K0Seg(Addr addr) 642022SN/A{ 652124SN/A#if !ALPHA_TLASER 662124SN/A if (addr & PAddrUncachedBit43) { 672022SN/A addr &= PAddrUncachedMask; 682124SN/A addr |= PAddrUncachedBit40; 692124SN/A } 702124SN/A#endif 712124SN/A return addr | AlphaISA::K0SegBase; 722124SN/A} 732124SN/A 742742Sksewell@umich.eduinline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 752742Sksewell@umich.eduinline Addr DTB_PTE_PPN(uint64_t reg) 762742Sksewell@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 772742Sksewell@umich.eduinline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 782742Sksewell@umich.eduinline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 792742Sksewell@umich.eduinline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 802742Sksewell@umich.eduinline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 812742Sksewell@umich.eduinline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 822742Sksewell@umich.eduinline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 832742Sksewell@umich.edu 842742Sksewell@umich.eduinline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 852742Sksewell@umich.eduinline Addr ITB_PTE_PPN(uint64_t reg) 862742Sksewell@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 872742Sksewell@umich.eduinline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 882742Sksewell@umich.eduinline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 892742Sksewell@umich.eduinline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 902742Sksewell@umich.eduinline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 912742Sksewell@umich.eduinline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 922022SN/A 932022SN/Ainline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 942124SN/A 952022SN/Ainline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 962124SN/Ainline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 972124SN/Ainline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 982124SN/A 992742Sksewell@umich.eduinline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 1002239SN/Ainline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1012124SN/Ainline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1022124SN/A 1032742Sksewell@umich.educonst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 1042742Sksewell@umich.educonst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 1052742Sksewell@umich.educonst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 1062742Sksewell@umich.educonst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 1072742Sksewell@umich.educonst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 1082742Sksewell@umich.educonst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 1092742Sksewell@umich.eduinline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 1102742Sksewell@umich.eduinline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 1112022SN/A 1122022SN/Aconst Addr PalBase = 0x4000; 1132124SN/Aconst Addr PalMax = 0x10000; 1142124SN/A 1152124SN/A/* namespace EV5 */ } 1162124SN/A 1172124SN/A#endif // __ARCH_ALPHA_EV5_HH__ 1182124SN/A