ev5.hh revision 1805 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_ALPHA_EV5_HH__
30#define __ARCH_ALPHA_EV5_HH__
31
32namespace EV5 {
33
34#ifdef ALPHA_TLASER
35const uint64_t AsnMask = ULL(0x7f);
36#else
37const uint64_t AsnMask = ULL(0xff);
38#endif
39
40const int VAddrImplBits = 43;
41const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
42const Addr VAddrUnImplMask = ~VAddrImplMask;
43inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
44inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; }
45inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
46inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
47inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
48
49#ifdef ALPHA_TLASER
50inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
51const int PAddrImplBits = 40;
52#else
53inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
54const int PAddrImplBits = 44; // for Tsunami
55#endif
56const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
57const Addr PAddrUncachedBit39 = ULL(0x8000000000);
58const Addr PAddrUncachedBit40 = ULL(0x10000000000);
59const Addr PAddrUncachedBit43 = ULL(0x80000000000);
60const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
61inline Addr Phys2K0Seg(Addr addr)
62{
63#ifndef ALPHA_TLASER
64    if (addr & PAddrUncachedBit43) {
65        addr &= PAddrUncachedMask;
66        addr |= PAddrUncachedBit40;
67    }
68#endif
69    return addr | AlphaISA::K0SegBase;
70}
71
72inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
73inline Addr DTB_PTE_PPN(uint64_t reg)
74{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
75inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
76inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
77inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
78inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
79inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
80inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
81
82inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
83inline Addr ITB_PTE_PPN(uint64_t reg)
84{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
85inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
86inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
87inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
88inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
89inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
90
91inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
92
93inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
94inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
95inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
96
97inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
98inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
99inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
100
101const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
102const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
103const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
104const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
105const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
106const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
107inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; }
108inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
109
110const Addr PalBase = 0x4000;
111const Addr PalMax = 0x10000;
112
113/* namespace EV5 */ }
114
115#endif // __ARCH_ALPHA_EV5_HH__
116