ev5.hh revision 1147
12686Sksewell@umich.edu/* $Id$ */ 22686Sksewell@umich.edu 35268Sksewell@umich.edu#ifndef __ARCH_ALPHA_EV5_HH__ 45268Sksewell@umich.edu#define __ARCH_ALPHA_EV5_HH__ 55268Sksewell@umich.edu 65268Sksewell@umich.edunamespace EV5 { 75268Sksewell@umich.edu 85268Sksewell@umich.edu#ifdef ALPHA_TLASER 95268Sksewell@umich.educonst uint64_t AsnMask = ULL(0x7f); 105268Sksewell@umich.edu#else 115268Sksewell@umich.educonst uint64_t AsnMask = ULL(0xff); 125268Sksewell@umich.edu#endif 135268Sksewell@umich.edu 145268Sksewell@umich.educonst int VAddrImplBits = 43; 155268Sksewell@umich.educonst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 165268Sksewell@umich.educonst Addr VAddrUnImplMask = ~VAddrImplMask; 175268Sksewell@umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 185268Sksewell@umich.eduinline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 195268Sksewell@umich.eduinline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 205268Sksewell@umich.eduinline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 215268Sksewell@umich.eduinline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 225268Sksewell@umich.edu 235268Sksewell@umich.edu#ifdef ALPHA_TLASER 245268Sksewell@umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 255268Sksewell@umich.educonst int PAddrImplBits = 40; 265268Sksewell@umich.edu#else 275268Sksewell@umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 285268Sksewell@umich.educonst int PAddrImplBits = 44; // for Tsunami 295268Sksewell@umich.edu#endif 302706Sksewell@umich.educonst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 312686Sksewell@umich.educonst Addr PAddrUncachedBit39 = ULL(0x8000000000); 322686Sksewell@umich.educonst Addr PAddrUncachedBit40 = ULL(0x10000000000); 332686Sksewell@umich.educonst Addr PAddrUncachedBit43 = ULL(0x80000000000); 342686Sksewell@umich.educonst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 352686Sksewell@umich.edu 362686Sksewell@umich.eduinline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 372686Sksewell@umich.eduinline Addr DTB_PTE_PPN(uint64_t reg) 382741Sksewell@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 392686Sksewell@umich.eduinline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 404661Sksewell@umich.eduinline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 412686Sksewell@umich.eduinline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 422686Sksewell@umich.eduinline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 432686Sksewell@umich.eduinline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 442686Sksewell@umich.eduinline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 454661Sksewell@umich.edu 464661Sksewell@umich.eduinline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 472686Sksewell@umich.eduinline Addr ITB_PTE_PPN(uint64_t reg) 482686Sksewell@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 492686Sksewell@umich.eduinline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 504661Sksewell@umich.eduinline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 514661Sksewell@umich.eduinline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 524661Sksewell@umich.eduinline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 534661Sksewell@umich.eduinline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 544661Sksewell@umich.edu 554661Sksewell@umich.eduinline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 564661Sksewell@umich.edu 574661Sksewell@umich.eduinline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 584661Sksewell@umich.eduinline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 594661Sksewell@umich.eduinline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 604661Sksewell@umich.edu 614661Sksewell@umich.eduinline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 624661Sksewell@umich.eduinline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 634661Sksewell@umich.eduinline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 644661Sksewell@umich.edu 654661Sksewell@umich.educonst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 664661Sksewell@umich.educonst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 672686Sksewell@umich.educonst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 682686Sksewell@umich.educonst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 692686Sksewell@umich.educonst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 702686Sksewell@umich.educonst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 714661Sksewell@umich.eduinline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 724661Sksewell@umich.eduinline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 734661Sksewell@umich.edu 744661Sksewell@umich.educonst Addr PalBase = 0x4000; 755269Sksewell@umich.educonst Addr PalMax = 0x10000; 764661Sksewell@umich.edu 775269Sksewell@umich.edu/* namespace EV5 */ } 784661Sksewell@umich.edu 794661Sksewell@umich.edu#endif // __ARCH_ALPHA_EV5_HH__ 804661Sksewell@umich.edu