sc_lv_base.cpp revision 12027:1eb7dc7aa10b
1/***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20/***************************************************************************** 21 22 sc_lv_base.cpp -- Arbitrary size logic vector class. 23 24 Original Author: Gene Bushuyev, Synopsys, Inc. 25 26 *****************************************************************************/ 27 28/***************************************************************************** 29 30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 31 changes you are making here. 32 33 Name, Affiliation, Date: 34 Description of Modification: 35 36 *****************************************************************************/ 37 38 39// $Log: sc_lv_base.cpp,v $ 40// Revision 1.2 2011/08/24 22:05:40 acg 41// Torsten Maehne: initialization changes to remove warnings. 42// 43// Revision 1.1.1.1 2006/12/15 20:20:04 acg 44// SystemC 2.3 45// 46// Revision 1.3 2006/01/13 18:53:53 acg 47// Andy Goodrich: added $Log command so that CVS comments are reproduced in 48// the source. 49// 50 51#include "sysc/datatypes/bit/sc_bit_ids.h" 52#include "sysc/datatypes/bit/sc_lv_base.h" 53 54 55namespace sc_dt 56{ 57 58// ---------------------------------------------------------------------------- 59// CLASS : sc_lv_base 60// 61// Arbitrary size logic vector base class. 62// ---------------------------------------------------------------------------- 63 64static const sc_digit data_array[] = 65 { SC_DIGIT_ZERO, ~SC_DIGIT_ZERO, SC_DIGIT_ZERO, ~SC_DIGIT_ZERO }; 66 67static const sc_digit ctrl_array[] = 68 { SC_DIGIT_ZERO, SC_DIGIT_ZERO, ~SC_DIGIT_ZERO, ~SC_DIGIT_ZERO }; 69 70 71void 72sc_lv_base::init( int length_, const sc_logic& init_value ) 73{ 74 // check the length 75 if( length_ <= 0 ) { 76 SC_REPORT_ERROR( sc_core::SC_ID_ZERO_LENGTH_, 0 ); 77 } 78 // allocate memory for the data and control words 79 m_len = length_; 80 m_size = (m_len - 1) / SC_DIGIT_SIZE + 1; 81 m_data = new sc_digit[m_size * 2]; 82 m_ctrl = m_data + m_size; 83 // initialize the bits to 'init_value' 84 sc_digit dw = data_array[init_value.value()]; 85 sc_digit cw = ctrl_array[init_value.value()]; 86 int sz = m_size; 87 for( int i = 0; i < sz; ++ i ) { 88 m_data[i] = dw; 89 m_ctrl[i] = cw; 90 } 91 clean_tail(); 92} 93 94 95void 96sc_lv_base::assign_from_string( const std::string& s ) 97{ 98 // s must have been converted to bin 99 int len = m_len; 100 int s_len = s.length() - 1; 101 int min_len = sc_min( len, s_len ); 102 int i = 0; 103 for( ; i < min_len; ++ i ) { 104 char c = s[s_len - i - 1]; 105 set_bit( i, sc_logic::char_to_logic[(int)c] ); 106 } 107 // if formatted, fill the rest with sign(s), otherwise fill with zeros 108 sc_logic_value_t fill = (s[s_len] == 'F' ? sc_logic_value_t( s[0] - '0' ) 109 : sc_logic_value_t( 0 )); 110 for( ; i < len; ++ i ) { 111 set_bit( i, fill ); 112 } 113} 114 115 116// constructors 117 118sc_lv_base::sc_lv_base( const char* a ) 119 : m_len( 0 ), m_size( 0 ), m_data( 0 ), m_ctrl( 0 ) 120{ 121 std::string s = convert_to_bin( a ); 122 init( s.length() - 1 ); 123 assign_from_string( s ); 124} 125 126sc_lv_base::sc_lv_base( const char* a, int length_ ) 127 : m_len( 0 ), m_size( 0 ), m_data( 0 ), m_ctrl( 0 ) 128{ 129 init( length_ ); 130 assign_from_string( convert_to_bin( a ) ); 131} 132 133sc_lv_base::sc_lv_base( const sc_lv_base& a ) 134 : sc_proxy<sc_lv_base>(), 135 m_len( a.m_len ), 136 m_size( a.m_size ), 137 m_data( new sc_digit[m_size * 2] ), 138 m_ctrl( m_data + m_size ) 139{ 140 // copy the bits 141 int sz = m_size; 142 for( int i = 0; i < sz; ++ i ) { 143 m_data[i] = a.m_data[i]; 144 m_ctrl[i] = a.m_ctrl[i]; 145 } 146} 147 148 149// assignment operators 150 151sc_lv_base& 152sc_lv_base::operator = ( const char* a ) 153{ 154 assign_from_string( convert_to_bin( a ) ); 155 return *this; 156} 157 158 159// returns true if logic vector contains only 0's and 1's 160 161bool 162sc_lv_base::is_01() const 163{ 164 int sz = m_size; 165 for( int i = 0; i < sz; ++ i ) { 166 if( m_ctrl[i] != 0 ) { 167 return false; 168 } 169 } 170 return true; 171} 172 173} // namespace sc_dt 174