ExtSlave.cc revision 11617:a51ae096ca25 
1// Copyright (c) 2015 ARM Limited
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35
36// Copyright 2009-2014 Sandia Coporation.  Under the terms
37// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
38// Government retains certain rights in this software.
39//
40// Copyright (c) 2009-2014, Sandia Corporation
41// All rights reserved.
42//
43// For license information, see the LICENSE file in the current directory.
44
45#include "gem5.hh"
46
47#include <core/sst_config.h>
48
49#include <sst/core/params.h>
50#include <sst/core/output.h>
51#include <sst/core/link.h>
52
53#ifdef fatal  // gem5 sets this
54#undef fatal
55#endif
56
57using namespace SST;
58using namespace SST::gem5;
59using namespace SST::MemHierarchy;
60
61ExtSlave::ExtSlave(gem5Component *g5c, Output &out,
62        ::ExternalSlave& port, std::string &name) :
63    Port(name, port),
64    comp(g5c), out(out), simPhase(CONSTRUCTION), initPackets(NULL),
65    link(comp->configureLink(name, new Event::Handler<ExtSlave>(this,
66                                              &ExtSlave::handleEvent)))
67{
68    if (!link) {
69        out.fatal(CALL_INFO, 1, "Failed to configure link %s\n", name.c_str());
70    }
71}
72
73void ExtSlave::init(unsigned phase)
74{
75    simPhase = INIT;
76    if (initPackets) {
77        while (!initPackets->empty()) {
78            link->sendInitData(initPackets->front());
79            initPackets->pop_front();
80        }
81        delete initPackets;
82        initPackets = NULL;
83    }
84}
85
86void
87ExtSlave::recvFunctional(PacketPtr pkt)
88{
89    if (simPhase == CONSTRUCTION) {
90        if (initPackets == NULL) {
91            initPackets = new std::list<MemEvent*>;
92        }
93        ::MemCmd::Command pktCmd = (::MemCmd::Command)pkt->cmd.toInt();
94        assert(pktCmd == ::MemCmd::WriteReq);
95        Addr a = pkt->getAddr();
96        MemEvent* ev = new MemEvent(comp, a, a, GetX);
97        ev->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
98        initPackets->push_back(ev);
99    } else {
100        panic("Functional accesses not allowed after construction phase");
101    }
102}
103
104bool
105ExtSlave::recvTimingReq(PacketPtr pkt)
106{
107    Command cmd;
108    switch ((::MemCmd::Command)pkt->cmd.toInt()) {
109    case ::MemCmd::HardPFReq:
110    case ::MemCmd::SoftPFReq:
111    case ::MemCmd::LoadLockedReq:
112    case ::MemCmd::ReadExReq:
113    case ::MemCmd::ReadReq:       cmd = GetS;   break;
114    case ::MemCmd::StoreCondReq:
115    case ::MemCmd::WriteReq:      cmd = GetX;   break;
116    default:
117        out.fatal(CALL_INFO, 1, "Don't know how to convert gem5 packet "
118                  "command %s to SST\n", pkt->cmd.toString().c_str());
119    }
120
121    auto ev = new MemEvent(comp, pkt->getAddr(), pkt->getAddr(), cmd);
122    ev->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
123    if ((::MemCmd::Command)pkt->cmd.toInt() == ::MemCmd::LoadLockedReq)
124        ev->setLoadLink();
125    else if ((::MemCmd::Command)pkt->cmd.toInt() == ::MemCmd::StoreCondReq)
126        ev->setStoreConditional();
127
128    if (pkt->req->isLockedRMW())   ev->setFlag(MemEvent::F_LOCKED);
129    if (pkt->req->isUncacheable()) ev->setFlag(MemEvent::F_NONCACHEABLE);
130    if (pkt->req->hasContextId())  ev->setGroupId(pkt->req->contextId());
131// Prefetches not working with SST; it maybe be dropping them, treating them
132// as not deserving of responses, or something else -- not sure yet.
133//  ev->setPrefetchFlag(pkt->req->isPrefetch());
134
135    if (simPhase == INIT) {
136        link->sendInitData(ev);
137        delete pkt->req;
138        delete pkt;
139    } else {
140        if (pkt->needsResponse()) {
141            PacketMap[ev->getID()] = pkt;
142        }
143        link->send(ev);
144    }
145    return true;
146}
147
148
149void
150ExtSlave::handleEvent(Event* ev)
151{
152    MemEvent* event = dynamic_cast<MemEvent*>(ev);
153    if (!event) {
154        out.fatal(CALL_INFO, 1, "ExtSlave handleEvent received non-MemEvent\n");
155        delete ev;
156        return;
157    }
158    Event::id_type id = event->getID();
159
160    PacketMap_t::iterator mi = PacketMap.find(id);
161    if (mi != PacketMap.end()) { // replying to prior request
162        PacketPtr pkt = mi->second;
163        PacketMap.erase(mi);
164
165        pkt->makeResponse();  // Convert to a response packet
166        pkt->setData(event->getPayload().data());
167
168        // Resolve the success of Store Conditionals
169        if (pkt->isLLSC() && pkt->isWrite()) {
170            pkt->req->setExtraData(event->isAtomic());
171        }
172
173        // Clear out bus delay notifications
174        pkt->headerDelay = pkt->payloadDelay = 0;
175
176        if (blocked() || !sendTimingResp(pkt)) {
177            respQ.push_back(pkt);
178        }
179    } else { // we can handle unexpected invalidates, but nothing else.
180        Command cmd = event->getCmd();
181        assert(cmd == Inv);
182
183        // make Req/Pkt for Snoop/no response needed
184        // presently no consideration for masterId, packet type, flags...
185        RequestPtr req = new Request(event->getAddr(), event->getSize(), 0, 0);
186        auto pkt = new Packet(req, ::MemCmd::InvalidateReq);
187
188        // Clear out bus delay notifications
189        pkt->headerDelay = pkt->payloadDelay = 0;
190
191        sendTimingSnoopReq(pkt);
192    }
193    delete event;
194}
195
196void
197ExtSlave::recvRespRetry()
198{
199    while (blocked() && sendTimingResp(respQ.front())) {
200        respQ.pop_front();
201    }
202}
203