ExtMaster.cc revision 11429:cf5af0cc3be4 
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35
36// Copyright 2009-2014 Sandia Coporation.  Under the terms
37// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
38// Government retains certain rights in this software.
39//
40// Copyright (c) 2009-2014, Sandia Corporation
41// All rights reserved.
42//
43// For license information, see the LICENSE file in the current directory.
44
45#include "gem5.hh"
46
47#ifdef fatal  // gem5 sets this
48#undef fatal
49#endif
50
51#include <sst_config.h>
52
53#include <mem/packet.hh>
54
55#include <sst/core/component.h>
56#include <sst/core/params.h>
57#include <sst/core/link.h>
58#include <sst/elements/memHierarchy/memNIC.h>
59
60using namespace SST;
61using namespace SST::gem5;
62using namespace SST::MemHierarchy;
63
64ExtMaster::ExtMaster(gem5Component *g, Output &o, ::ExternalMaster& p,
65        std::string &n) :
66    Port(n, p), out(o), port(p), simPhase(CONSTRUCTION),
67    gem5(g), name(n)
68{
69    Params _p; // will be ignored
70    nic = dynamic_cast<MemNIC*>(gem5->loadModuleWithComponent("memHierarchy.memNIC", g, _p));
71
72    MemNIC::ComponentInfo ci;
73    ci.num_vcs = 1;
74    ci.link_port = "network";
75    ci.link_bandwidth = "16GB/s";
76    ci.link_inbuf_size = "1KB";
77    ci.link_outbuf_size = "1KB";
78    ci.network_addr = 0; // hard coded at the moment
79    ci.type = MemNIC::TypeDirectoryCtrl;
80    nic->moduleInit(ci, new Event::Handler<ExtMaster>
81                                          (this, &ExtMaster::handleEvent));
82}
83
84void
85ExtMaster::init(unsigned phase)
86{
87    simPhase = INIT;
88
89    if (phase == 0) {
90        assert(nic);
91        for (auto range : getAddrRanges()) {
92            MemNIC::ComponentTypeInfo ti;
93            ti.rangeStart = range.start();
94            ti.rangeEnd = range.end();
95            ti.interleaveSize = 0;
96            ti.interleaveStep = 0;
97            nic->addTypeInfo(ti);
98            ranges.insert(range);
99        }
100    }
101
102    nic->init(phase);
103}
104
105void
106ExtMaster::setup(void)
107{
108    nic->setup();
109
110    simPhase = RUN;
111}
112
113void
114ExtMaster::finish(void)
115{
116    nic->finish();
117}
118
119void
120ExtMaster::clock(void)
121{
122    nic->clock();
123}
124
125void
126ExtMaster::handleEvent(SST::Event* event)
127{
128    if (simPhase == CONSTRUCTION) {
129        out.fatal(CALL_INFO, 1, "received Event during Construction phase\n");
130    }
131
132    MemEvent *ev = dynamic_cast<MemEvent*>(event);
133    if (!ev) {
134        out.fatal(CALL_INFO, 1, "Can't handle non-MemEvent Event's\n");
135    }
136
137    Command cmdI = ev->getCmd(); // command in - SST
138    MemCmd::Command cmdO;        // command out - gem5
139    bool data = false;
140
141    switch (cmdI) {
142        case GetS:      cmdO = MemCmd::ReadReq;                break;
143        case GetX:      cmdO = MemCmd::WriteReq;  data = true; break;
144        case GetSEx:
145        case PutS:
146        case PutM:
147        case PutE:
148        case PutX:
149        case PutXE:
150        case Inv:
151        case FetchInv:
152        case FetchInvX:
153
154        case NACK:
155
156        case NULLCMD:
157        case GetSResp:
158        case GetXResp:
159        case FetchResp:
160        case FetchXResp:
161            out.fatal(CALL_INFO, 1, "Don't know how to convert "
162                                    "SST command %s to gem5\n",
163                      CommandString[cmdI]);
164    }
165
166    Request::FlagsType flags = 0;
167    if (ev->queryFlag(MemEvent::F_LOCKED))
168        flags |= Request::LOCKED_RMW;
169    if (ev->queryFlag(MemEvent::F_NONCACHEABLE))
170        flags |= Request::UNCACHEABLE;
171    if (ev->isLoadLink()) {
172        assert(cmdI == GetS);
173        cmdO = MemCmd::LoadLockedReq;
174    } else if (ev->isStoreConditional()) {
175        assert(cmdI == GetX);
176        cmdO = MemCmd::StoreCondReq;
177    }
178
179    auto req = new Request(ev->getAddr(), ev->getSize(), flags, 0);
180    req->setThreadContext(ev->getGroupId(), 0);
181
182    auto pkt = new Packet(req, cmdO);
183    pkt->allocate();
184    if (data) {
185        pkt->setData(ev->getPayload().data());
186    }
187    pkt->pushSenderState(new SenderState(ev));
188
189    if (blocked() || !sendTimingReq(pkt))
190        sendQ.push_back(pkt);
191}
192
193bool
194ExtMaster::recvTimingResp(PacketPtr pkt) {
195    if (simPhase == INIT) {
196        out.fatal(CALL_INFO, 1, "not prepared to handle INIT-phase traffic\n");
197    }
198
199    // get original SST packet from gem5 SenderState
200    auto senderState = dynamic_cast<SenderState*>(pkt->popSenderState());
201    if (!senderState)
202        out.fatal(CALL_INFO, 1, "gem5 senderState corrupt\n");
203
204    // make (new) response packet, discard (old) original request
205    MemEvent* ev = senderState->event;
206    delete senderState;
207
208    MemEvent* resp = ev->makeResponse();
209    delete ev;
210
211    // copy the payload and then destroy gem5 packet
212    resp->setPayload(pkt->getSize(), pkt->getPtr<uint8_t>());
213    delete pkt->req;
214    delete pkt;
215
216    nic->send(resp);
217    return true;
218}
219
220void
221ExtMaster::recvReqRetry() {
222    while (blocked() && sendTimingReq(sendQ.front())) {
223        sendQ.pop_front();
224    }
225}
226
227void
228ExtMaster::recvRangeChange() {
229    for (auto range : getAddrRanges()) {
230        if (ranges.find(range) == ranges.end()) { // i.e. if not found,
231            MemNIC::ComponentTypeInfo ti;      // indicating a new range.
232            ti.rangeStart = range.start();
233            ti.rangeEnd = range.end();
234            ti.interleaveSize = 0;
235            ti.interleaveStep = 0;
236            nic->addTypeInfo(ti);
237            ranges.insert(range);
238        }
239    }
240}
241