mmu.cc revision 10915:71ace17ccb3d
1955SN/A/*
2955SN/A * Copyright (c) 2014-2015 ARM Limited
312230Sgiacomo.travaglini@arm.com * All rights reserved
49812Sandreas.hansson@arm.com *
59812Sandreas.hansson@arm.com * Licensed under the Apache License, Version 2.0 (the "License");
69812Sandreas.hansson@arm.com * you may not use this file except in compliance with the License.
79812Sandreas.hansson@arm.com * You may obtain a copy of the License at
89812Sandreas.hansson@arm.com *
99812Sandreas.hansson@arm.com *     http://www.apache.org/licenses/LICENSE-2.0
109812Sandreas.hansson@arm.com *
119812Sandreas.hansson@arm.com * Unless required by applicable law or agreed to in writing, software
129812Sandreas.hansson@arm.com * distributed under the License is distributed on an "AS IS" BASIS,
139812Sandreas.hansson@arm.com * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
149812Sandreas.hansson@arm.com * See the License for the specific language governing permissions and
157816Ssteve.reinhardt@amd.com * limitations under the License.
165871Snate@binkert.org *
171762SN/A * Authors: Andreas Sandberg
18955SN/A */
19955SN/A
20955SN/A#include "mmu.hh"
21955SN/A
22955SN/A#include "gpu.hh"
23955SN/A#include "regutils.hh"
24955SN/A
25955SN/Anamespace NoMali {
26955SN/A
27955SN/AMMU::MMU(GPU &_gpu)
28955SN/A    : GPUBlockInt(_gpu,
29955SN/A                  RegAddr(MMU_IRQ_RAWSTAT),
30955SN/A                  RegAddr(MMU_IRQ_CLEAR),
31955SN/A                  RegAddr(MMU_IRQ_MASK),
32955SN/A                  RegAddr(MMU_IRQ_STATUS)),
33955SN/A      regs(BLOCK_NUM_REGS)
34955SN/A{
35955SN/A}
36955SN/A
37955SN/AMMU::~MMU()
38955SN/A{
39955SN/A}
40955SN/A
41955SN/Avoid
422665Ssaidi@eecs.umich.eduMMU::writeReg(RegAddr addr, uint32_t value)
432665Ssaidi@eecs.umich.edu{
445863Snate@binkert.org    switch (addr.value) {
45955SN/A      case MMU_IRQ_RAWSTAT:
46955SN/A      case MMU_IRQ_CLEAR:
47955SN/A      case MMU_IRQ_MASK:
48955SN/A      case MMU_IRQ_STATUS:
49955SN/A        GPUBlockInt::writeReg(addr, value);
508878Ssteve.reinhardt@amd.com        break;
512632Sstever@eecs.umich.edu
528878Ssteve.reinhardt@amd.com      default:
532632Sstever@eecs.umich.edu        // Ignore writes by default
54955SN/A        break;
558878Ssteve.reinhardt@amd.com    };
562632Sstever@eecs.umich.edu}
572761Sstever@eecs.umich.edu
582632Sstever@eecs.umich.eduvoid
592632Sstever@eecs.umich.eduMMU::onInterrupt(int set)
602632Sstever@eecs.umich.edu{
612761Sstever@eecs.umich.edu    gpu.intMMU(set);
622761Sstever@eecs.umich.edu}
632761Sstever@eecs.umich.edu
648878Ssteve.reinhardt@amd.com}
658878Ssteve.reinhardt@amd.com