gpucontrol.hh revision 10915 
1/*
2 * Copyright (c) 2014-2015 ARM Limited
3 * All rights reserved
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 *     http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 * Authors: Andreas Sandberg
18 */
19
20#ifndef _LIBNOMALIMODEL_GPUCONTROL_HH
21#define _LIBNOMALIMODEL_GPUCONTROL_HH
22
23#include <vector>
24
25#include "types.hh"
26#include "gpublock.hh"
27
28namespace NoMali {
29
30class GPU;
31
32/**
33 * Limited GPU control block implementation.
34 *
35 * This is a minimal implementation of the Midgard GPU control
36 * block. It contains the stuff necessary to do command decoding and
37 * dispatch, interrupt handling, and GPU block ready handling.
38 *
39 * An actual GPU implementation should specialize this class to setup
40 * the following registers from the reset() method:
41 * <ul>
42 *   <li>GPU_ID
43 *   <li>Feature registers (XX_FEATURES)
44 *   <li>Present registers (XX_PRESENT)
45 *   <li>Thread discovery (THREAD_XX)
46 *   <li>Present registers (XX_PRESENT)
47 * </ul>
48 */
49class GPUControl
50    : public GPUBlockInt
51{
52  public:
53    GPUControl(GPU &_gpu);
54    virtual ~GPUControl();
55
56    virtual void reset() override = 0;
57
58    void writeReg(RegAddr idx, uint32_t value) override;
59
60  protected:
61    void onInterrupt(int set) override;
62
63    /**
64     * @{
65     * @name GPU control block commands
66     */
67
68    /**
69     * Control command dispatcher.
70     *
71     * This method is called whenever there is a write to the
72     * GPU_COMMAND register. The method uses a lookup table to call
73     * the right command handling method.
74     *
75     * @param cmd Command number (see the Midgard architecture
76     * specification)
77     */
78    virtual void gpuCommand(uint32_t cmd);
79    /**
80     * Command handler for No-ops.
81     *
82     * @param cmd Command number (see the Midgard architecture
83     * specification)
84     */
85    virtual void cmdNop(uint32_t cmd);
86    /**
87     * Command handler for GPU-wide hard resets
88     *
89     * @param cmd Command number (see the Midgard architecture
90     * specification)
91     */
92    virtual void cmdHardReset(uint32_t cmd);
93    /**
94     * Command handler for GPU-wide soft resets
95     *
96     * @param cmd Command number (see the Midgard architecture
97     * specification)
98     */
99    virtual void cmdSoftReset(uint32_t cmd);
100    /**
101     * Command handler for performance counter clear operations.
102     *
103     * @param cmd Command number (see the Midgard architecture
104     * specification)
105     */
106    virtual void cmdPerfCntClear(uint32_t cmd);
107    /**
108     * Command handler for performance counter sample operations.
109     *
110     * @param cmd Command number (see the Midgard architecture
111     * specification)
112     */
113    virtual void cmdPerfCntSample(uint32_t cmd);
114    /**
115     * Command handler for cycle counter start operations.
116     *
117     * @param cmd Command number (see the Midgard architecture
118     * specification)
119     */
120    virtual void cmdCycleCountStart(uint32_t cmd);
121    /**
122     * Command handler for cycle counter stop operations.
123     *
124     * @param cmd Command number (see the Midgard architecture
125     * specification)
126     */
127    virtual void cmdCycleCountStop(uint32_t cmd);
128    /**
129     * Command handler for cache cleaning operations.
130     *
131     * @param cmd Command number (see the Midgard architecture
132     * specification)
133     */
134    virtual void cmdCleanCaches(uint32_t cmd);
135    /**
136     * Command handler for cache clean and invalidate operations.
137     *
138     * @param cmd Command number (see the Midgard architecture
139     * specification)
140     */
141    virtual void cmdCleanInvCaches(uint32_t cmd);
142
143    /** @} */
144
145  protected:
146    typedef void (GPUControl::*cmd_t)(uint32_t);
147    /**
148     * Mapping between command IDs and command handling methods.
149     *
150     * @note The order of this vector <i>MUST</i> correspond to the
151     * GPU control command IDs in the Midgard architecture
152     * specification.
153     */
154    static const std::vector<cmd_t> cmds;
155};
156
157}
158
159#endif // _LIBNOMALIMODEL_GPUCONTROL_HH
160