gpublock.cc revision 10915
110915Sandreas.sandberg@arm.com/* 210915Sandreas.sandberg@arm.com * Copyright (c) 2014-2015 ARM Limited 310915Sandreas.sandberg@arm.com * All rights reserved 410915Sandreas.sandberg@arm.com * 510915Sandreas.sandberg@arm.com * Licensed under the Apache License, Version 2.0 (the "License"); 610915Sandreas.sandberg@arm.com * you may not use this file except in compliance with the License. 710915Sandreas.sandberg@arm.com * You may obtain a copy of the License at 810915Sandreas.sandberg@arm.com * 910915Sandreas.sandberg@arm.com * http://www.apache.org/licenses/LICENSE-2.0 1010915Sandreas.sandberg@arm.com * 1110915Sandreas.sandberg@arm.com * Unless required by applicable law or agreed to in writing, software 1210915Sandreas.sandberg@arm.com * distributed under the License is distributed on an "AS IS" BASIS, 1310915Sandreas.sandberg@arm.com * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 1410915Sandreas.sandberg@arm.com * See the License for the specific language governing permissions and 1510915Sandreas.sandberg@arm.com * limitations under the License. 1610915Sandreas.sandberg@arm.com * 1710915Sandreas.sandberg@arm.com * Authors: Andreas Sandberg 1810915Sandreas.sandberg@arm.com */ 1910915Sandreas.sandberg@arm.com 2010915Sandreas.sandberg@arm.com#include "gpublock.hh" 2110915Sandreas.sandberg@arm.com 2210915Sandreas.sandberg@arm.com#include "gpu.hh" 2310915Sandreas.sandberg@arm.com#include "regutils.hh" 2410915Sandreas.sandberg@arm.com 2510915Sandreas.sandberg@arm.comnamespace NoMali { 2610915Sandreas.sandberg@arm.com 2710915Sandreas.sandberg@arm.comGPUBlock::GPUBlock(GPU &_gpu) 2810915Sandreas.sandberg@arm.com : gpu(_gpu), regs(BLOCK_NUM_REGS) 2910915Sandreas.sandberg@arm.com{ 3010915Sandreas.sandberg@arm.com} 3110915Sandreas.sandberg@arm.com 3210915Sandreas.sandberg@arm.comGPUBlock::GPUBlock(GPU &_gpu, RegVector::size_type no_regs) 3310915Sandreas.sandberg@arm.com : gpu(_gpu), regs(no_regs) 3410915Sandreas.sandberg@arm.com{ 3510915Sandreas.sandberg@arm.com} 3610915Sandreas.sandberg@arm.com 3710915Sandreas.sandberg@arm.comGPUBlock::GPUBlock(GPUBlock &&rhs) 3810915Sandreas.sandberg@arm.com : gpu(rhs.gpu), 3910915Sandreas.sandberg@arm.com regs(std::move(rhs.regs)) 4010915Sandreas.sandberg@arm.com{ 4110915Sandreas.sandberg@arm.com} 4210915Sandreas.sandberg@arm.com 4310915Sandreas.sandberg@arm.comGPUBlock::~GPUBlock() 4410915Sandreas.sandberg@arm.com{ 4510915Sandreas.sandberg@arm.com} 4610915Sandreas.sandberg@arm.com 4710915Sandreas.sandberg@arm.comvoid 4810915Sandreas.sandberg@arm.comGPUBlock::reset() 4910915Sandreas.sandberg@arm.com{ 5010915Sandreas.sandberg@arm.com for (auto &r : regs) 5110915Sandreas.sandberg@arm.com r = 0; 5210915Sandreas.sandberg@arm.com} 5310915Sandreas.sandberg@arm.com 5410915Sandreas.sandberg@arm.comuint32_t 5510915Sandreas.sandberg@arm.comGPUBlock::readReg(RegAddr addr) 5610915Sandreas.sandberg@arm.com{ 5710915Sandreas.sandberg@arm.com return readRegRaw(addr); 5810915Sandreas.sandberg@arm.com} 5910915Sandreas.sandberg@arm.com 6010915Sandreas.sandberg@arm.comvoid 6110915Sandreas.sandberg@arm.comGPUBlock::writeReg(RegAddr addr, uint32_t value) 6210915Sandreas.sandberg@arm.com{ 6310915Sandreas.sandberg@arm.com writeRegRaw(addr, value); 6410915Sandreas.sandberg@arm.com} 6510915Sandreas.sandberg@arm.com 6610915Sandreas.sandberg@arm.comuint32_t 6710915Sandreas.sandberg@arm.comGPUBlock::readRegRaw(RegAddr addr) 6810915Sandreas.sandberg@arm.com{ 6910915Sandreas.sandberg@arm.com return regs[addr]; 7010915Sandreas.sandberg@arm.com} 7110915Sandreas.sandberg@arm.com 7210915Sandreas.sandberg@arm.comvoid 7310915Sandreas.sandberg@arm.comGPUBlock::writeRegRaw(RegAddr addr, uint32_t value) 7410915Sandreas.sandberg@arm.com{ 7510915Sandreas.sandberg@arm.com regs[addr] = value; 7610915Sandreas.sandberg@arm.com} 7710915Sandreas.sandberg@arm.com 7810915Sandreas.sandberg@arm.com 7910915Sandreas.sandberg@arm.com 8010915Sandreas.sandberg@arm.comGPUBlockInt::GPUBlockInt(GPU &_gpu, 8110915Sandreas.sandberg@arm.com const RegAddr &irq_raw_stat, 8210915Sandreas.sandberg@arm.com const RegAddr &irq_clear, 8310915Sandreas.sandberg@arm.com const RegAddr &irq_mask, 8410915Sandreas.sandberg@arm.com const RegAddr &irq_stat) 8510915Sandreas.sandberg@arm.com : GPUBlock(_gpu), 8610915Sandreas.sandberg@arm.com addrIrqRawStat(irq_raw_stat), addrIrqClear(irq_clear), 8710915Sandreas.sandberg@arm.com addrIrqMask(irq_mask), addrIrqStat(irq_stat) 8810915Sandreas.sandberg@arm.com{ 8910915Sandreas.sandberg@arm.com} 9010915Sandreas.sandberg@arm.com 9110915Sandreas.sandberg@arm.comGPUBlockInt::~GPUBlockInt() 9210915Sandreas.sandberg@arm.com{ 9310915Sandreas.sandberg@arm.com} 9410915Sandreas.sandberg@arm.com 9510915Sandreas.sandberg@arm.comuint32_t 9610915Sandreas.sandberg@arm.comGPUBlockInt::readReg(RegAddr addr) 9710915Sandreas.sandberg@arm.com{ 9810915Sandreas.sandberg@arm.com if (addr == addrIrqStat) { 9910915Sandreas.sandberg@arm.com return irqStatus(); 10010915Sandreas.sandberg@arm.com } else { 10110915Sandreas.sandberg@arm.com return GPUBlock::readReg(addr); 10210915Sandreas.sandberg@arm.com } 10310915Sandreas.sandberg@arm.com} 10410915Sandreas.sandberg@arm.com 10510915Sandreas.sandberg@arm.comvoid 10610915Sandreas.sandberg@arm.comGPUBlockInt::writeReg(RegAddr addr, uint32_t value) 10710915Sandreas.sandberg@arm.com{ 10810915Sandreas.sandberg@arm.com if (addr == addrIrqRawStat) { 10910915Sandreas.sandberg@arm.com raiseInterrupt(value); 11010915Sandreas.sandberg@arm.com } else if (addr == addrIrqClear) { 11110915Sandreas.sandberg@arm.com clearInterrupt(value); 11210915Sandreas.sandberg@arm.com } else if (addr == addrIrqMask ) { 11310915Sandreas.sandberg@arm.com const bool old_int(intAsserted()); 11410915Sandreas.sandberg@arm.com GPUBlock::writeReg(addr, value); 11510915Sandreas.sandberg@arm.com if (old_int != intAsserted()) 11610915Sandreas.sandberg@arm.com onInterrupt(intAsserted()); 11710915Sandreas.sandberg@arm.com } else if (addr == addrIrqStat ) { 11810915Sandreas.sandberg@arm.com // Ignore writes to the IRQ status register 11910915Sandreas.sandberg@arm.com } else { 12010915Sandreas.sandberg@arm.com // Handle addrIrqMask & defaults 12110915Sandreas.sandberg@arm.com GPUBlock::writeReg(addr, value); 12210915Sandreas.sandberg@arm.com } 12310915Sandreas.sandberg@arm.com} 12410915Sandreas.sandberg@arm.com 12510915Sandreas.sandberg@arm.com 12610915Sandreas.sandberg@arm.com 12710915Sandreas.sandberg@arm.comvoid 12810915Sandreas.sandberg@arm.comGPUBlockInt::raiseInterrupt(uint32_t ints) 12910915Sandreas.sandberg@arm.com{ 13010915Sandreas.sandberg@arm.com const bool old_int(intAsserted()); 13110915Sandreas.sandberg@arm.com 13210915Sandreas.sandberg@arm.com regs[addrIrqRawStat] |= ints; 13310915Sandreas.sandberg@arm.com // Is the interrupt line going high? 13410915Sandreas.sandberg@arm.com if (!old_int && intAsserted()) 13510915Sandreas.sandberg@arm.com onInterrupt(1); 13610915Sandreas.sandberg@arm.com} 13710915Sandreas.sandberg@arm.com 13810915Sandreas.sandberg@arm.comvoid 13910915Sandreas.sandberg@arm.comGPUBlockInt::clearInterrupt(uint32_t ints) 14010915Sandreas.sandberg@arm.com{ 14110915Sandreas.sandberg@arm.com const bool old_int(intAsserted()); 14210915Sandreas.sandberg@arm.com 14310915Sandreas.sandberg@arm.com regs[addrIrqRawStat] &= ~ints; 14410915Sandreas.sandberg@arm.com // Is the interrupt line going low? 14510915Sandreas.sandberg@arm.com if (old_int && !intAsserted()) 14610915Sandreas.sandberg@arm.com onInterrupt(0); 14710915Sandreas.sandberg@arm.com} 14810915Sandreas.sandberg@arm.com 14910915Sandreas.sandberg@arm.comuint32_t 15010915Sandreas.sandberg@arm.comGPUBlockInt::irqStatus() const 15110915Sandreas.sandberg@arm.com{ 15210915Sandreas.sandberg@arm.com return regs[addrIrqRawStat] & regs[addrIrqMask]; 15310915Sandreas.sandberg@arm.com} 15410915Sandreas.sandberg@arm.com 15510915Sandreas.sandberg@arm.com 15610915Sandreas.sandberg@arm.com} 157