core.h revision 10234:5cb711fa6176 
1/*****************************************************************************
2 *                                McPAT
3 *                      SOFTWARE LICENSE AGREEMENT
4 *            Copyright 2012 Hewlett-Packard Development Company, L.P.
5 *            Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
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31 ***************************************************************************/
32
33
34#ifndef CORE_H_
35#define CORE_H_
36
37#include "array.h"
38#include "basic_components.h"
39#include "cacheunit.h"
40#include "interconnect.h"
41#include "logic.h"
42#include "parameter.h"
43
44// Macros used in the various core-related classes
45#define NUM_SOURCE_OPERANDS 2
46#define NUM_INT_INST_SOURCE_OPERANDS 2
47
48class BranchPredictorParameters {
49public:
50    int assoc;
51    int nbanks;
52    int local_l1_predictor_size;
53    int local_l2_predictor_size;
54    int local_predictor_entries;
55    int global_predictor_bits;
56    int global_predictor_entries;
57    int chooser_predictor_bits;
58    int chooser_predictor_entries;
59};
60
61class BranchPredictor : public McPATComponent {
62public:
63    ArrayST* globalBPT;
64    ArrayST* localBPT;
65    ArrayST* L1_localBPT;
66    ArrayST* L2_localBPT;
67    ArrayST* chooser;
68    ArrayST* RAS;
69
70    InputParameter interface_ip;
71    CoreParameters core_params;
72    CoreStatistics core_stats;
73    BranchPredictorParameters branch_pred_params;
74    double scktRatio, chip_PR_overhead, macro_PR_overhead;
75    bool exist;
76
77    BranchPredictor(XMLNode* _xml_data, InputParameter* interface_ip_,
78                    const CoreParameters & _core_params,
79                    const CoreStatistics & _core_stats,
80                    bool exsit = true);
81    void set_params_stats();
82    void computeEnergy();
83    void displayData(uint32_t indent = 0, int plevel = 100);
84    ~BranchPredictor();
85};
86
87class InstFetchParameters {
88public:
89    int btb_size;
90    int btb_block_size;
91    int btb_assoc;
92    int btb_num_banks;
93    int btb_latency;
94    int btb_throughput;
95    int btb_rw_ports;
96};
97
98class InstFetchStatistics {
99public:
100    double btb_read_accesses;
101    double btb_write_accesses;
102};
103
104class InstFetchU : public McPATComponent {
105public:
106    CacheUnit* icache;
107    ArrayST* IB;
108    ArrayST* BTB;
109    BranchPredictor* BPT;
110    InstructionDecoder* ID_inst;
111    InstructionDecoder* ID_operand;
112    InstructionDecoder* ID_misc;
113
114    InputParameter interface_ip;
115    CoreParameters core_params;
116    CoreStatistics core_stats;
117    InstFetchParameters inst_fetch_params;
118    InstFetchStatistics inst_fetch_stats;
119    double scktRatio, chip_PR_overhead, macro_PR_overhead;
120    enum Cache_policy cache_p;
121    bool exist;
122
123    InstFetchU(XMLNode* _xml_data, InputParameter* interface_ip_,
124               const CoreParameters & _core_params,
125               const CoreStatistics & _core_stats,
126               bool exsit = true);
127    void set_params_stats();
128    void computeEnergy();
129    void displayData(uint32_t indent = 0, int plevel = 100);
130    ~InstFetchU();
131};
132
133
134class SchedulerU : public McPATComponent {
135public:
136    static int ROB_STATUS_BITS;
137
138    ArrayST* int_inst_window;
139    ArrayST* fp_inst_window;
140    ArrayST* ROB;
141    selection_logic* int_instruction_selection;
142    selection_logic* fp_instruction_selection;
143
144    InputParameter interface_ip;
145    CoreParameters core_params;
146    CoreStatistics core_stats;
147    double scktRatio, chip_PR_overhead, macro_PR_overhead;
148    double Iw_height, fp_Iw_height, ROB_height;
149    bool exist;
150
151    SchedulerU(XMLNode* _xml_data, InputParameter* interface_ip_,
152               const CoreParameters & _core_params,
153               const CoreStatistics & _core_stats,
154               bool exist_ = true);
155    void computeEnergy();
156    void displayData(uint32_t indent = 0, int plevel = 100);
157    ~SchedulerU();
158};
159
160class RENAMINGU : public McPATComponent {
161public:
162    ArrayST* iFRAT;
163    ArrayST* fFRAT;
164    ArrayST* iRRAT;
165    ArrayST* fRRAT;
166    ArrayST* ifreeL;
167    ArrayST* ffreeL;
168    dep_resource_conflict_check* idcl;
169    dep_resource_conflict_check* fdcl;
170    ArrayST* RAHT;
171
172    InputParameter interface_ip;
173    CoreParameters core_params;
174    CoreStatistics core_stats;
175    bool exist;
176
177    RENAMINGU(XMLNode* _xml_data, InputParameter* interface_ip_,
178              const CoreParameters & _core_params,
179              const CoreStatistics & _core_stats,
180              bool exist_ = true);
181    void computeEnergy();
182    void displayData(uint32_t indent = 0, int plevel = 100);
183    ~RENAMINGU();
184};
185
186class LoadStoreU : public McPATComponent {
187public:
188    CacheUnit* dcache;
189    ArrayST* LSQ;
190    ArrayST* LoadQ;
191
192    InputParameter interface_ip;
193    CoreParameters core_params;
194    CoreStatistics core_stats;
195    enum Cache_policy cache_p;
196    double scktRatio, chip_PR_overhead, macro_PR_overhead;
197    double lsq_height;
198    bool exist;
199
200    LoadStoreU(XMLNode* _xml_data, InputParameter* interface_ip_,
201               const CoreParameters & _core_params,
202               const CoreStatistics & _core_stats,
203               bool exist_ = true);
204    void computeEnergy();
205    void displayData(uint32_t indent = 0, int plevel = 100);
206    ~LoadStoreU();
207};
208
209class MemoryManagementParams {
210public:
211    int itlb_number_entries;
212    double itlb_latency;
213    double itlb_throughput;
214    int itlb_assoc;
215    int itlb_nbanks;
216    int dtlb_number_entries;
217    double dtlb_latency;
218    double dtlb_throughput;
219    int dtlb_assoc;
220    int dtlb_nbanks;
221};
222
223class MemoryManagementStats {
224public:
225    double itlb_total_accesses;
226    double itlb_total_misses;
227    double itlb_conflicts;
228    double dtlb_read_accesses;
229    double dtlb_read_misses;
230    double dtlb_write_accesses;
231    double dtlb_write_misses;
232    double dtlb_conflicts;
233};
234
235class MemManU : public McPATComponent {
236public:
237    ArrayST* itlb;
238    ArrayST* dtlb;
239
240    InputParameter interface_ip;
241    CoreParameters core_params;
242    CoreStatistics core_stats;
243    MemoryManagementParams mem_man_params;
244    MemoryManagementStats mem_man_stats;
245    double scktRatio, chip_PR_overhead, macro_PR_overhead;
246    bool exist;
247
248    MemManU(XMLNode* _xml_data, InputParameter* interface_ip_,
249            const CoreParameters & _core_params,
250            const CoreStatistics & _core_stats, bool exist_ = true);
251    void set_params_stats();
252    void computeEnergy();
253    void displayData(uint32_t indent = 0, int plevel = 100);
254    ~MemManU();
255};
256
257class RegFU : public McPATComponent {
258public:
259    static int RFWIN_ACCESS_MULTIPLIER;
260
261    ArrayST* IRF;
262    ArrayST* FRF;
263    ArrayST* RFWIN;
264
265    InputParameter interface_ip;
266    CoreParameters core_params;
267    CoreStatistics core_stats;
268    double scktRatio, chip_PR_overhead, macro_PR_overhead;
269    double int_regfile_height, fp_regfile_height;
270    bool exist;
271
272    RegFU(XMLNode* _xml_data,
273          InputParameter* interface_ip_, const CoreParameters & _core_params,
274          const CoreStatistics & _core_stats,
275          bool exist_ = true);
276    void computeEnergy();
277    void displayData(uint32_t indent = 0, int plevel = 100);
278    ~RegFU();
279};
280
281class EXECU : public McPATComponent {
282public:
283    RegFU* rfu;
284    SchedulerU* scheu;
285    FunctionalUnit* fp_u;
286    FunctionalUnit* exeu;
287    FunctionalUnit* mul;
288    Interconnect* int_bypass;
289    Interconnect* intTagBypass;
290    Interconnect* int_mul_bypass;
291    Interconnect* intTag_mul_Bypass;
292    Interconnect* fp_bypass;
293    Interconnect* fpTagBypass;
294
295    InputParameter interface_ip;
296    double scktRatio, chip_PR_overhead, macro_PR_overhead;
297    double lsq_height;
298    CoreParameters core_params;
299    CoreStatistics core_stats;
300    bool exist;
301
302    EXECU(XMLNode* _xml_data, InputParameter* interface_ip_,
303          double lsq_height_, const CoreParameters & _core_params,
304          const CoreStatistics & _core_stats, bool exist_ = true);
305    void computeEnergy();
306    void displayData(uint32_t indent = 0, int plevel = 100);
307    ~EXECU();
308};
309
310
311class Core : public McPATComponent {
312public:
313    InstFetchU* ifu;
314    LoadStoreU* lsu;
315    MemManU* mmu;
316    EXECU* exu;
317    RENAMINGU* rnu;
318    Pipeline* corepipe;
319    UndiffCore* undiffCore;
320    CacheUnit* l2cache;
321
322    int ithCore;
323    InputParameter interface_ip;
324    double scktRatio, chip_PR_overhead, macro_PR_overhead;
325    CoreParameters core_params;
326    CoreStatistics core_stats;
327
328    // TODO: Migrate component ID handling into the XML data to remove this
329    //       ithCore variable
330    Core(XMLNode* _xml_data, int _ithCore, InputParameter* interface_ip_);
331    void initialize_params();
332    void initialize_stats();
333    void set_core_param();
334    void computeEnergy();
335    ~Core();
336};
337
338#endif /* CORE_H_ */
339