core.h revision 10234
110152Satgutier@umich.edu/***************************************************************************** 210152Satgutier@umich.edu * McPAT 310152Satgutier@umich.edu * SOFTWARE LICENSE AGREEMENT 410152Satgutier@umich.edu * Copyright 2012 Hewlett-Packard Development Company, L.P. 510234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 610152Satgutier@umich.edu * All Rights Reserved 710152Satgutier@umich.edu * 810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1510152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1610152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1710152Satgutier@umich.edu * this software without specific prior written permission. 1810152Satgutier@umich.edu 1910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2910234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3010152Satgutier@umich.edu * 3110152Satgutier@umich.edu ***************************************************************************/ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu 3410152Satgutier@umich.edu#ifndef CORE_H_ 3510152Satgutier@umich.edu#define CORE_H_ 3610152Satgutier@umich.edu 3710152Satgutier@umich.edu#include "array.h" 3810152Satgutier@umich.edu#include "basic_components.h" 3910234Syasuko.eckert@amd.com#include "cacheunit.h" 4010152Satgutier@umich.edu#include "interconnect.h" 4110152Satgutier@umich.edu#include "logic.h" 4210152Satgutier@umich.edu#include "parameter.h" 4310152Satgutier@umich.edu 4410234Syasuko.eckert@amd.com// Macros used in the various core-related classes 4510234Syasuko.eckert@amd.com#define NUM_SOURCE_OPERANDS 2 4610234Syasuko.eckert@amd.com#define NUM_INT_INST_SOURCE_OPERANDS 2 4710152Satgutier@umich.edu 4810234Syasuko.eckert@amd.comclass BranchPredictorParameters { 4910234Syasuko.eckert@amd.compublic: 5010234Syasuko.eckert@amd.com int assoc; 5110234Syasuko.eckert@amd.com int nbanks; 5210234Syasuko.eckert@amd.com int local_l1_predictor_size; 5310234Syasuko.eckert@amd.com int local_l2_predictor_size; 5410234Syasuko.eckert@amd.com int local_predictor_entries; 5510234Syasuko.eckert@amd.com int global_predictor_bits; 5610234Syasuko.eckert@amd.com int global_predictor_entries; 5710234Syasuko.eckert@amd.com int chooser_predictor_bits; 5810234Syasuko.eckert@amd.com int chooser_predictor_entries; 5910152Satgutier@umich.edu}; 6010152Satgutier@umich.edu 6110234Syasuko.eckert@amd.comclass BranchPredictor : public McPATComponent { 6210234Syasuko.eckert@amd.compublic: 6310234Syasuko.eckert@amd.com ArrayST* globalBPT; 6410234Syasuko.eckert@amd.com ArrayST* localBPT; 6510234Syasuko.eckert@amd.com ArrayST* L1_localBPT; 6610234Syasuko.eckert@amd.com ArrayST* L2_localBPT; 6710234Syasuko.eckert@amd.com ArrayST* chooser; 6810234Syasuko.eckert@amd.com ArrayST* RAS; 6910152Satgutier@umich.edu 7010234Syasuko.eckert@amd.com InputParameter interface_ip; 7110234Syasuko.eckert@amd.com CoreParameters core_params; 7210234Syasuko.eckert@amd.com CoreStatistics core_stats; 7310234Syasuko.eckert@amd.com BranchPredictorParameters branch_pred_params; 7410234Syasuko.eckert@amd.com double scktRatio, chip_PR_overhead, macro_PR_overhead; 7510234Syasuko.eckert@amd.com bool exist; 7610152Satgutier@umich.edu 7710234Syasuko.eckert@amd.com BranchPredictor(XMLNode* _xml_data, InputParameter* interface_ip_, 7810234Syasuko.eckert@amd.com const CoreParameters & _core_params, 7910234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, 8010234Syasuko.eckert@amd.com bool exsit = true); 8110234Syasuko.eckert@amd.com void set_params_stats(); 8210234Syasuko.eckert@amd.com void computeEnergy(); 8310234Syasuko.eckert@amd.com void displayData(uint32_t indent = 0, int plevel = 100); 8410234Syasuko.eckert@amd.com ~BranchPredictor(); 8510152Satgutier@umich.edu}; 8610152Satgutier@umich.edu 8710234Syasuko.eckert@amd.comclass InstFetchParameters { 8810234Syasuko.eckert@amd.compublic: 8910234Syasuko.eckert@amd.com int btb_size; 9010234Syasuko.eckert@amd.com int btb_block_size; 9110234Syasuko.eckert@amd.com int btb_assoc; 9210234Syasuko.eckert@amd.com int btb_num_banks; 9310234Syasuko.eckert@amd.com int btb_latency; 9410234Syasuko.eckert@amd.com int btb_throughput; 9510234Syasuko.eckert@amd.com int btb_rw_ports; 9610234Syasuko.eckert@amd.com}; 9710152Satgutier@umich.edu 9810234Syasuko.eckert@amd.comclass InstFetchStatistics { 9910234Syasuko.eckert@amd.compublic: 10010234Syasuko.eckert@amd.com double btb_read_accesses; 10110234Syasuko.eckert@amd.com double btb_write_accesses; 10210234Syasuko.eckert@amd.com}; 10310152Satgutier@umich.edu 10410234Syasuko.eckert@amd.comclass InstFetchU : public McPATComponent { 10510234Syasuko.eckert@amd.compublic: 10610234Syasuko.eckert@amd.com CacheUnit* icache; 10710234Syasuko.eckert@amd.com ArrayST* IB; 10810234Syasuko.eckert@amd.com ArrayST* BTB; 10910234Syasuko.eckert@amd.com BranchPredictor* BPT; 11010234Syasuko.eckert@amd.com InstructionDecoder* ID_inst; 11110234Syasuko.eckert@amd.com InstructionDecoder* ID_operand; 11210234Syasuko.eckert@amd.com InstructionDecoder* ID_misc; 11310234Syasuko.eckert@amd.com 11410234Syasuko.eckert@amd.com InputParameter interface_ip; 11510234Syasuko.eckert@amd.com CoreParameters core_params; 11610234Syasuko.eckert@amd.com CoreStatistics core_stats; 11710234Syasuko.eckert@amd.com InstFetchParameters inst_fetch_params; 11810234Syasuko.eckert@amd.com InstFetchStatistics inst_fetch_stats; 11910234Syasuko.eckert@amd.com double scktRatio, chip_PR_overhead, macro_PR_overhead; 12010234Syasuko.eckert@amd.com enum Cache_policy cache_p; 12110152Satgutier@umich.edu bool exist; 12210152Satgutier@umich.edu 12310234Syasuko.eckert@amd.com InstFetchU(XMLNode* _xml_data, InputParameter* interface_ip_, 12410234Syasuko.eckert@amd.com const CoreParameters & _core_params, 12510234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, 12610234Syasuko.eckert@amd.com bool exsit = true); 12710234Syasuko.eckert@amd.com void set_params_stats(); 12810234Syasuko.eckert@amd.com void computeEnergy(); 12910234Syasuko.eckert@amd.com void displayData(uint32_t indent = 0, int plevel = 100); 13010234Syasuko.eckert@amd.com ~InstFetchU(); 13110152Satgutier@umich.edu}; 13210152Satgutier@umich.edu 13310152Satgutier@umich.edu 13410234Syasuko.eckert@amd.comclass SchedulerU : public McPATComponent { 13510234Syasuko.eckert@amd.compublic: 13610234Syasuko.eckert@amd.com static int ROB_STATUS_BITS; 13710152Satgutier@umich.edu 13810234Syasuko.eckert@amd.com ArrayST* int_inst_window; 13910234Syasuko.eckert@amd.com ArrayST* fp_inst_window; 14010234Syasuko.eckert@amd.com ArrayST* ROB; 14110234Syasuko.eckert@amd.com selection_logic* int_instruction_selection; 14210234Syasuko.eckert@amd.com selection_logic* fp_instruction_selection; 14310152Satgutier@umich.edu 14410234Syasuko.eckert@amd.com InputParameter interface_ip; 14510234Syasuko.eckert@amd.com CoreParameters core_params; 14610234Syasuko.eckert@amd.com CoreStatistics core_stats; 14710234Syasuko.eckert@amd.com double scktRatio, chip_PR_overhead, macro_PR_overhead; 14810234Syasuko.eckert@amd.com double Iw_height, fp_Iw_height, ROB_height; 14910234Syasuko.eckert@amd.com bool exist; 15010234Syasuko.eckert@amd.com 15110234Syasuko.eckert@amd.com SchedulerU(XMLNode* _xml_data, InputParameter* interface_ip_, 15210234Syasuko.eckert@amd.com const CoreParameters & _core_params, 15310234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, 15410234Syasuko.eckert@amd.com bool exist_ = true); 15510234Syasuko.eckert@amd.com void computeEnergy(); 15610234Syasuko.eckert@amd.com void displayData(uint32_t indent = 0, int plevel = 100); 15710234Syasuko.eckert@amd.com ~SchedulerU(); 15810152Satgutier@umich.edu}; 15910152Satgutier@umich.edu 16010234Syasuko.eckert@amd.comclass RENAMINGU : public McPATComponent { 16110234Syasuko.eckert@amd.compublic: 16210234Syasuko.eckert@amd.com ArrayST* iFRAT; 16310234Syasuko.eckert@amd.com ArrayST* fFRAT; 16410234Syasuko.eckert@amd.com ArrayST* iRRAT; 16510234Syasuko.eckert@amd.com ArrayST* fRRAT; 16610234Syasuko.eckert@amd.com ArrayST* ifreeL; 16710234Syasuko.eckert@amd.com ArrayST* ffreeL; 16810234Syasuko.eckert@amd.com dep_resource_conflict_check* idcl; 16910234Syasuko.eckert@amd.com dep_resource_conflict_check* fdcl; 17010234Syasuko.eckert@amd.com ArrayST* RAHT; 17110152Satgutier@umich.edu 17210234Syasuko.eckert@amd.com InputParameter interface_ip; 17310234Syasuko.eckert@amd.com CoreParameters core_params; 17410234Syasuko.eckert@amd.com CoreStatistics core_stats; 17510234Syasuko.eckert@amd.com bool exist; 17610152Satgutier@umich.edu 17710234Syasuko.eckert@amd.com RENAMINGU(XMLNode* _xml_data, InputParameter* interface_ip_, 17810234Syasuko.eckert@amd.com const CoreParameters & _core_params, 17910234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, 18010234Syasuko.eckert@amd.com bool exist_ = true); 18110234Syasuko.eckert@amd.com void computeEnergy(); 18210234Syasuko.eckert@amd.com void displayData(uint32_t indent = 0, int plevel = 100); 18310234Syasuko.eckert@amd.com ~RENAMINGU(); 18410152Satgutier@umich.edu}; 18510152Satgutier@umich.edu 18610234Syasuko.eckert@amd.comclass LoadStoreU : public McPATComponent { 18710234Syasuko.eckert@amd.compublic: 18810234Syasuko.eckert@amd.com CacheUnit* dcache; 18910234Syasuko.eckert@amd.com ArrayST* LSQ; 19010234Syasuko.eckert@amd.com ArrayST* LoadQ; 19110152Satgutier@umich.edu 19210234Syasuko.eckert@amd.com InputParameter interface_ip; 19310234Syasuko.eckert@amd.com CoreParameters core_params; 19410234Syasuko.eckert@amd.com CoreStatistics core_stats; 19510234Syasuko.eckert@amd.com enum Cache_policy cache_p; 19610234Syasuko.eckert@amd.com double scktRatio, chip_PR_overhead, macro_PR_overhead; 19710234Syasuko.eckert@amd.com double lsq_height; 19810234Syasuko.eckert@amd.com bool exist; 19910152Satgutier@umich.edu 20010234Syasuko.eckert@amd.com LoadStoreU(XMLNode* _xml_data, InputParameter* interface_ip_, 20110234Syasuko.eckert@amd.com const CoreParameters & _core_params, 20210234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, 20310234Syasuko.eckert@amd.com bool exist_ = true); 20410234Syasuko.eckert@amd.com void computeEnergy(); 20510234Syasuko.eckert@amd.com void displayData(uint32_t indent = 0, int plevel = 100); 20610234Syasuko.eckert@amd.com ~LoadStoreU(); 20710152Satgutier@umich.edu}; 20810152Satgutier@umich.edu 20910234Syasuko.eckert@amd.comclass MemoryManagementParams { 21010234Syasuko.eckert@amd.compublic: 21110234Syasuko.eckert@amd.com int itlb_number_entries; 21210234Syasuko.eckert@amd.com double itlb_latency; 21310234Syasuko.eckert@amd.com double itlb_throughput; 21410234Syasuko.eckert@amd.com int itlb_assoc; 21510234Syasuko.eckert@amd.com int itlb_nbanks; 21610234Syasuko.eckert@amd.com int dtlb_number_entries; 21710234Syasuko.eckert@amd.com double dtlb_latency; 21810234Syasuko.eckert@amd.com double dtlb_throughput; 21910234Syasuko.eckert@amd.com int dtlb_assoc; 22010234Syasuko.eckert@amd.com int dtlb_nbanks; 22110152Satgutier@umich.edu}; 22210152Satgutier@umich.edu 22310234Syasuko.eckert@amd.comclass MemoryManagementStats { 22410234Syasuko.eckert@amd.compublic: 22510234Syasuko.eckert@amd.com double itlb_total_accesses; 22610234Syasuko.eckert@amd.com double itlb_total_misses; 22710234Syasuko.eckert@amd.com double itlb_conflicts; 22810234Syasuko.eckert@amd.com double dtlb_read_accesses; 22910234Syasuko.eckert@amd.com double dtlb_read_misses; 23010234Syasuko.eckert@amd.com double dtlb_write_accesses; 23110234Syasuko.eckert@amd.com double dtlb_write_misses; 23210234Syasuko.eckert@amd.com double dtlb_conflicts; 23310152Satgutier@umich.edu}; 23410152Satgutier@umich.edu 23510234Syasuko.eckert@amd.comclass MemManU : public McPATComponent { 23610234Syasuko.eckert@amd.compublic: 23710234Syasuko.eckert@amd.com ArrayST* itlb; 23810234Syasuko.eckert@amd.com ArrayST* dtlb; 23910152Satgutier@umich.edu 24010234Syasuko.eckert@amd.com InputParameter interface_ip; 24110234Syasuko.eckert@amd.com CoreParameters core_params; 24210234Syasuko.eckert@amd.com CoreStatistics core_stats; 24310234Syasuko.eckert@amd.com MemoryManagementParams mem_man_params; 24410234Syasuko.eckert@amd.com MemoryManagementStats mem_man_stats; 24510234Syasuko.eckert@amd.com double scktRatio, chip_PR_overhead, macro_PR_overhead; 24610234Syasuko.eckert@amd.com bool exist; 24710152Satgutier@umich.edu 24810234Syasuko.eckert@amd.com MemManU(XMLNode* _xml_data, InputParameter* interface_ip_, 24910234Syasuko.eckert@amd.com const CoreParameters & _core_params, 25010234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, bool exist_ = true); 25110234Syasuko.eckert@amd.com void set_params_stats(); 25210234Syasuko.eckert@amd.com void computeEnergy(); 25310234Syasuko.eckert@amd.com void displayData(uint32_t indent = 0, int plevel = 100); 25410234Syasuko.eckert@amd.com ~MemManU(); 25510234Syasuko.eckert@amd.com}; 25610234Syasuko.eckert@amd.com 25710234Syasuko.eckert@amd.comclass RegFU : public McPATComponent { 25810234Syasuko.eckert@amd.compublic: 25910234Syasuko.eckert@amd.com static int RFWIN_ACCESS_MULTIPLIER; 26010234Syasuko.eckert@amd.com 26110234Syasuko.eckert@amd.com ArrayST* IRF; 26210234Syasuko.eckert@amd.com ArrayST* FRF; 26310234Syasuko.eckert@amd.com ArrayST* RFWIN; 26410234Syasuko.eckert@amd.com 26510234Syasuko.eckert@amd.com InputParameter interface_ip; 26610234Syasuko.eckert@amd.com CoreParameters core_params; 26710234Syasuko.eckert@amd.com CoreStatistics core_stats; 26810234Syasuko.eckert@amd.com double scktRatio, chip_PR_overhead, macro_PR_overhead; 26910234Syasuko.eckert@amd.com double int_regfile_height, fp_regfile_height; 27010234Syasuko.eckert@amd.com bool exist; 27110234Syasuko.eckert@amd.com 27210234Syasuko.eckert@amd.com RegFU(XMLNode* _xml_data, 27310234Syasuko.eckert@amd.com InputParameter* interface_ip_, const CoreParameters & _core_params, 27410234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, 27510234Syasuko.eckert@amd.com bool exist_ = true); 27610234Syasuko.eckert@amd.com void computeEnergy(); 27710234Syasuko.eckert@amd.com void displayData(uint32_t indent = 0, int plevel = 100); 27810234Syasuko.eckert@amd.com ~RegFU(); 27910234Syasuko.eckert@amd.com}; 28010234Syasuko.eckert@amd.com 28110234Syasuko.eckert@amd.comclass EXECU : public McPATComponent { 28210234Syasuko.eckert@amd.compublic: 28310234Syasuko.eckert@amd.com RegFU* rfu; 28410234Syasuko.eckert@amd.com SchedulerU* scheu; 28510234Syasuko.eckert@amd.com FunctionalUnit* fp_u; 28610234Syasuko.eckert@amd.com FunctionalUnit* exeu; 28710234Syasuko.eckert@amd.com FunctionalUnit* mul; 28810234Syasuko.eckert@amd.com Interconnect* int_bypass; 28910234Syasuko.eckert@amd.com Interconnect* intTagBypass; 29010234Syasuko.eckert@amd.com Interconnect* int_mul_bypass; 29110234Syasuko.eckert@amd.com Interconnect* intTag_mul_Bypass; 29210234Syasuko.eckert@amd.com Interconnect* fp_bypass; 29310234Syasuko.eckert@amd.com Interconnect* fpTagBypass; 29410234Syasuko.eckert@amd.com 29510234Syasuko.eckert@amd.com InputParameter interface_ip; 29610234Syasuko.eckert@amd.com double scktRatio, chip_PR_overhead, macro_PR_overhead; 29710234Syasuko.eckert@amd.com double lsq_height; 29810234Syasuko.eckert@amd.com CoreParameters core_params; 29910234Syasuko.eckert@amd.com CoreStatistics core_stats; 30010234Syasuko.eckert@amd.com bool exist; 30110234Syasuko.eckert@amd.com 30210234Syasuko.eckert@amd.com EXECU(XMLNode* _xml_data, InputParameter* interface_ip_, 30310234Syasuko.eckert@amd.com double lsq_height_, const CoreParameters & _core_params, 30410234Syasuko.eckert@amd.com const CoreStatistics & _core_stats, bool exist_ = true); 30510234Syasuko.eckert@amd.com void computeEnergy(); 30610234Syasuko.eckert@amd.com void displayData(uint32_t indent = 0, int plevel = 100); 30710234Syasuko.eckert@amd.com ~EXECU(); 30810234Syasuko.eckert@amd.com}; 30910234Syasuko.eckert@amd.com 31010234Syasuko.eckert@amd.com 31110234Syasuko.eckert@amd.comclass Core : public McPATComponent { 31210234Syasuko.eckert@amd.compublic: 31310234Syasuko.eckert@amd.com InstFetchU* ifu; 31410234Syasuko.eckert@amd.com LoadStoreU* lsu; 31510234Syasuko.eckert@amd.com MemManU* mmu; 31610234Syasuko.eckert@amd.com EXECU* exu; 31710234Syasuko.eckert@amd.com RENAMINGU* rnu; 31810234Syasuko.eckert@amd.com Pipeline* corepipe; 31910234Syasuko.eckert@amd.com UndiffCore* undiffCore; 32010234Syasuko.eckert@amd.com CacheUnit* l2cache; 32110234Syasuko.eckert@amd.com 32210234Syasuko.eckert@amd.com int ithCore; 32310234Syasuko.eckert@amd.com InputParameter interface_ip; 32410234Syasuko.eckert@amd.com double scktRatio, chip_PR_overhead, macro_PR_overhead; 32510234Syasuko.eckert@amd.com CoreParameters core_params; 32610234Syasuko.eckert@amd.com CoreStatistics core_stats; 32710234Syasuko.eckert@amd.com 32810234Syasuko.eckert@amd.com // TODO: Migrate component ID handling into the XML data to remove this 32910234Syasuko.eckert@amd.com // ithCore variable 33010234Syasuko.eckert@amd.com Core(XMLNode* _xml_data, int _ithCore, InputParameter* interface_ip_); 33110234Syasuko.eckert@amd.com void initialize_params(); 33210234Syasuko.eckert@amd.com void initialize_stats(); 33310234Syasuko.eckert@amd.com void set_core_param(); 33410234Syasuko.eckert@amd.com void computeEnergy(); 33510234Syasuko.eckert@amd.com ~Core(); 33610152Satgutier@umich.edu}; 33710152Satgutier@umich.edu 33810152Satgutier@umich.edu#endif /* CORE_H_ */ 339