decoder.h revision 10152 
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31
32
33#ifndef __DECODER_H__
34#define __DECODER_H__
35
36#include <vector>
37
38#include "area.h"
39#include "component.h"
40#include "parameter.h"
41
42using namespace std;
43
44
45class Decoder : public Component
46{
47  public:
48    Decoder(
49        int _num_dec_signals,
50        bool flag_way_select,
51        double _C_ld_dec_out,
52        double _R_wire_dec_out,
53        bool fully_assoc_,
54        bool is_dram_,
55        bool is_wl_tr_,
56        const Area & cell_);
57
58    bool   exist;
59    int    num_in_signals;
60    double C_ld_dec_out;
61    double R_wire_dec_out;
62    int    num_gates;
63    int    num_gates_min;
64    double w_dec_n[MAX_NUMBER_GATES_STAGE];
65    double w_dec_p[MAX_NUMBER_GATES_STAGE];
66    double delay;
67    //powerDef power;
68    bool   fully_assoc;
69    bool   is_dram;
70    bool   is_wl_tr;
71    const  Area & cell;
72
73
74    void   compute_widths();
75    void   compute_area();
76    double compute_delays(double inrisetime);  // return outrisetime
77
78    void leakage_feedback(double temperature);
79};
80
81
82
83class PredecBlk : public Component
84{
85 public:
86  PredecBlk(
87      int num_dec_signals,
88      Decoder * dec,
89      double C_wire_predec_blk_out,
90      double R_wire_predec_blk_out,
91      int    num_dec_per_predec,
92      bool   is_dram_,
93      bool   is_blk1);
94
95  Decoder * dec;
96  bool exist;
97  int number_input_addr_bits;
98  double C_ld_predec_blk_out;
99  double R_wire_predec_blk_out;
100  int branch_effort_nand2_gate_output;
101  int branch_effort_nand3_gate_output;
102  bool   flag_two_unique_paths;
103  int flag_L2_gate;
104  int number_inputs_L1_gate;
105  int number_gates_L1_nand2_path;
106  int number_gates_L1_nand3_path;
107  int number_gates_L2;
108  int min_number_gates_L1;
109  int min_number_gates_L2;
110  int num_L1_active_nand2_path;
111  int num_L1_active_nand3_path;
112  double w_L1_nand2_n[MAX_NUMBER_GATES_STAGE];
113  double w_L1_nand2_p[MAX_NUMBER_GATES_STAGE];
114  double w_L1_nand3_n[MAX_NUMBER_GATES_STAGE];
115  double w_L1_nand3_p[MAX_NUMBER_GATES_STAGE];
116  double w_L2_n[MAX_NUMBER_GATES_STAGE];
117  double w_L2_p[MAX_NUMBER_GATES_STAGE];
118  double delay_nand2_path;
119  double delay_nand3_path;
120  powerDef power_nand2_path;
121  powerDef power_nand3_path;
122  powerDef power_L2;
123
124  bool is_dram_;
125
126  void compute_widths();
127  void compute_area();
128
129  void leakage_feedback(double temperature);
130
131  pair<double, double> compute_delays(pair<double, double> inrisetime); // <nand2, nand3>
132  // return <outrise_nand2, outrise_nand3>
133};
134
135
136class PredecBlkDrv : public Component
137{
138 public:
139  PredecBlkDrv(
140      int   way_select,
141      PredecBlk * blk_,
142      bool  is_dram);
143
144  int flag_driver_exists;
145  int number_input_addr_bits;
146  int number_gates_nand2_path;
147  int number_gates_nand3_path;
148  int min_number_gates;
149  int num_buffers_driving_1_nand2_load;
150  int num_buffers_driving_2_nand2_load;
151  int num_buffers_driving_4_nand2_load;
152  int num_buffers_driving_2_nand3_load;
153  int num_buffers_driving_8_nand3_load;
154  int num_buffers_nand3_path;
155  double c_load_nand2_path_out;
156  double c_load_nand3_path_out;
157  double r_load_nand2_path_out;
158  double r_load_nand3_path_out;
159  double width_nand2_path_n[MAX_NUMBER_GATES_STAGE];
160  double width_nand2_path_p[MAX_NUMBER_GATES_STAGE];
161  double width_nand3_path_n[MAX_NUMBER_GATES_STAGE];
162  double width_nand3_path_p[MAX_NUMBER_GATES_STAGE];
163  double delay_nand2_path;
164  double delay_nand3_path;
165  powerDef power_nand2_path;
166  powerDef power_nand3_path;
167
168  PredecBlk * blk;
169  Decoder   * dec;
170  bool  is_dram_;
171  int   way_select;
172
173  void compute_widths();
174  void compute_area();
175
176  void leakage_feedback(double temperature);
177
178
179  pair<double, double> compute_delays(
180      double inrisetime_nand2_path,
181      double inrisetime_nand3_path);  // return <outrise_nand2, outrise_nand3>
182
183  inline int num_addr_bits_nand2_path()
184  {
185    return num_buffers_driving_1_nand2_load +
186           num_buffers_driving_2_nand2_load +
187           num_buffers_driving_4_nand2_load;
188  }
189  inline int num_addr_bits_nand3_path()
190  {
191    return num_buffers_driving_2_nand3_load +
192           num_buffers_driving_8_nand3_load;
193  }
194  double get_rdOp_dynamic_E(int num_act_mats_hor_dir);
195};
196
197
198
199class Predec : public Component
200{
201  public:
202    Predec(
203        PredecBlkDrv * drv1,
204        PredecBlkDrv * drv2);
205
206    double compute_delays(double inrisetime);  // return outrisetime
207
208    void leakage_feedback(double temperature);
209    PredecBlk    * blk1;
210    PredecBlk    * blk2;
211    PredecBlkDrv * drv1;
212    PredecBlkDrv * drv2;
213
214    powerDef block_power;
215    powerDef driver_power;
216
217  private:
218    // returns <delay, risetime>
219    pair<double, double> get_max_delay_before_decoder(
220        pair<double, double> input_pair1,
221        pair<double, double> input_pair2);
222};
223
224
225
226class Driver : public Component
227{
228 public:
229  Driver(double c_gate_load_, double c_wire_load_, double r_wire_load_, bool is_dram);
230
231  int    number_gates;
232  int    min_number_gates;
233  double width_n[MAX_NUMBER_GATES_STAGE];
234  double width_p[MAX_NUMBER_GATES_STAGE];
235  double c_gate_load;
236  double c_wire_load;
237  double r_wire_load;
238  double delay;
239  powerDef power;
240  bool   is_dram_;
241
242  void   compute_widths();
243  double compute_delay(double inrisetime);
244};
245
246
247#endif
248