crossbar.cc revision 10234
16019Shines@cs.fsu.edu/***************************************************************************** 27399SAli.Saidi@ARM.com * McPAT/CACTI 37399SAli.Saidi@ARM.com * SOFTWARE LICENSE AGREEMENT 47399SAli.Saidi@ARM.com * Copyright 2012 Hewlett-Packard Development Company, L.P. 57399SAli.Saidi@ARM.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 67399SAli.Saidi@ARM.com * All Rights Reserved 77399SAli.Saidi@ARM.com * 87399SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 97399SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 107399SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 117399SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 127399SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 137399SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 146019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 156019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 166019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 176019Shines@cs.fsu.edu * this software without specific prior written permission. 186019Shines@cs.fsu.edu 196019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 206019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 216019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 226019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 236019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 246019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 256019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 266019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 276019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 286019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 296019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 306019Shines@cs.fsu.edu * 316019Shines@cs.fsu.edu ***************************************************************************/ 326019Shines@cs.fsu.edu 336019Shines@cs.fsu.edu#include "crossbar.h" 346019Shines@cs.fsu.edu 356019Shines@cs.fsu.edu#define ASPECT_THRESHOLD .8 366019Shines@cs.fsu.edu#define ADJ 1 376019Shines@cs.fsu.edu 386019Shines@cs.fsu.eduCrossbar::Crossbar( 396019Shines@cs.fsu.edu double n_inp_, 407399SAli.Saidi@ARM.com double n_out_, 416019Shines@cs.fsu.edu double flit_size_, 426019Shines@cs.fsu.edu TechnologyParameter::DeviceType *dt 436019Shines@cs.fsu.edu): n_inp(n_inp_), n_out(n_out_), flit_size(flit_size_), deviceType(dt) { 446019Shines@cs.fsu.edu min_w_pmos = deviceType->n_to_p_eff_curr_drv_ratio * g_tp.min_w_nmos_; 456019Shines@cs.fsu.edu Vdd = dt->Vdd; 466019Shines@cs.fsu.edu CB_ADJ = 1; 476019Shines@cs.fsu.edu} 486019Shines@cs.fsu.edu 498229Snate@binkert.orgCrossbar::~Crossbar() {} 506019Shines@cs.fsu.edu 516019Shines@cs.fsu.edudouble Crossbar::output_buffer() { 526019Shines@cs.fsu.edu 536019Shines@cs.fsu.edu //Wire winit(4, 4); 546116Snate@binkert.org double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch; 557878Sgblack@eecs.umich.edu Wire w1(g_ip->wt, l_eff); 566019Shines@cs.fsu.edu //double s1 = w1.repeater_size *l_eff*ADJ/w1.repeater_spacing; 576019Shines@cs.fsu.edu double s1 = w1.repeater_size * (l_eff < w1.repeater_spacing ? 586019Shines@cs.fsu.edu l_eff * ADJ / w1.repeater_spacing : ADJ); 596019Shines@cs.fsu.edu double pton_size = deviceType->n_to_p_eff_curr_drv_ratio; 606019Shines@cs.fsu.edu // the model assumes input capacitance of the wire driver = input capacitance of nand + nor = input cap of the driver transistor 616019Shines@cs.fsu.edu TriS1 = s1 * (1 + pton_size) / (2 + pton_size + 1 + 2 * pton_size); 627404SAli.Saidi@ARM.com TriS2 = s1; //driver transistor 637404SAli.Saidi@ARM.com 646019Shines@cs.fsu.edu if (TriS1 < 1) 656019Shines@cs.fsu.edu TriS1 = 1; 667294Sgblack@eecs.umich.edu 677294Sgblack@eecs.umich.edu double input_cap = gate_C(TriS1 * (2 * min_w_pmos + g_tp.min_w_nmos_), 0) + 687639Sgblack@eecs.umich.edu gate_C(TriS1 * (min_w_pmos + 2 * g_tp.min_w_nmos_), 0); 697294Sgblack@eecs.umich.edu// input_cap += drain_C_(TriS1*g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + 707294Sgblack@eecs.umich.edu// drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def)*2 + 717294Sgblack@eecs.umich.edu// gate_C(TriS2*g_tp.min_w_nmos_, 0)+ 727294Sgblack@eecs.umich.edu// drain_C_(TriS1*min_w_pmos, NCH, 1, 1, g_tp.cell_h_def)*2 + 737294Sgblack@eecs.umich.edu// drain_C_(TriS1*min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + 747639Sgblack@eecs.umich.edu// gate_C(TriS2*min_w_pmos, 0); 757639Sgblack@eecs.umich.edu tri_int_cap = drain_C_(TriS1 * g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + 767294Sgblack@eecs.umich.edu drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) * 2 + 777639Sgblack@eecs.umich.edu gate_C(TriS2 * g_tp.min_w_nmos_, 0) + 787404SAli.Saidi@ARM.com drain_C_(TriS1 * min_w_pmos, NCH, 1, 1, g_tp.cell_h_def) * 2 + 797639Sgblack@eecs.umich.edu drain_C_(TriS1 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def) + 807294Sgblack@eecs.umich.edu gate_C(TriS2 * min_w_pmos, 0); 817294Sgblack@eecs.umich.edu double output_cap = drain_C_(TriS2 * g_tp.min_w_nmos_, NCH, 1, 1, 827294Sgblack@eecs.umich.edu g_tp.cell_h_def) + 837639Sgblack@eecs.umich.edu drain_C_(TriS2 * min_w_pmos, PCH, 1, 1, g_tp.cell_h_def); 847294Sgblack@eecs.umich.edu double ctr_cap = gate_C(TriS2 * (min_w_pmos + g_tp.min_w_nmos_), 0); 856019Shines@cs.fsu.edu 866019Shines@cs.fsu.edu tri_inp_cap = input_cap; 877799Sgblack@eecs.umich.edu tri_out_cap = output_cap; 887799Sgblack@eecs.umich.edu tri_ctr_cap = ctr_cap; 897406SAli.Saidi@ARM.com return input_cap + output_cap + ctr_cap; 907799Sgblack@eecs.umich.edu} 917436Sdam.sunwoo@arm.com 927406SAli.Saidi@ARM.comvoid Crossbar::compute_power() { 937404SAli.Saidi@ARM.com 947406SAli.Saidi@ARM.com Wire winit(4, 4); 956019Shines@cs.fsu.edu double tri_cap = output_buffer(); 967694SAli.Saidi@ARM.com assert(tri_cap > 0); 977694SAli.Saidi@ARM.com //area of a tristate logic 987694SAli.Saidi@ARM.com double g_area = compute_gate_area(INV, 1, TriS2 * g_tp.min_w_nmos_, 997694SAli.Saidi@ARM.com TriS2 * min_w_pmos, g_tp.cell_h_def); 1007694SAli.Saidi@ARM.com g_area *= 2; // to model area of output transistors 1017694SAli.Saidi@ARM.com g_area += compute_gate_area (NAND, 2, TriS1 * 2 * g_tp.min_w_nmos_, 1027694SAli.Saidi@ARM.com TriS1 * min_w_pmos, g_tp.cell_h_def); 1036019Shines@cs.fsu.edu g_area += compute_gate_area (NOR, 2, TriS1 * g_tp.min_w_nmos_, 1047399SAli.Saidi@ARM.com TriS1 * 2 * min_w_pmos, g_tp.cell_h_def); 1057734SAli.Saidi@ARM.com double width /*per tristate*/ = g_area / (CB_ADJ * g_tp.cell_h_def); 1067734SAli.Saidi@ARM.com // effective no. of tristate buffers that need to be laid side by side 1077734SAli.Saidi@ARM.com int ntri = (int)ceil(g_tp.cell_h_def / (g_tp.wire_outside_mat.pitch)); 1087734SAli.Saidi@ARM.com double wire_len = MAX(width * ntri * n_out, 1097734SAli.Saidi@ARM.com flit_size * g_tp.wire_outside_mat.pitch * n_out); 1107734SAli.Saidi@ARM.com Wire w1(g_ip->wt, wire_len); 1117734SAli.Saidi@ARM.com 1127734SAli.Saidi@ARM.com area.w = wire_len; 1137734SAli.Saidi@ARM.com area.h = g_tp.wire_outside_mat.pitch * n_inp * flit_size * CB_ADJ; 1147734SAli.Saidi@ARM.com Wire w2(g_ip->wt, area.h); 1157734SAli.Saidi@ARM.com 1167734SAli.Saidi@ARM.com double aspect_ratio_cb = (area.h / area.w) * (n_out / n_inp); 1177734SAli.Saidi@ARM.com if (aspect_ratio_cb > 1) aspect_ratio_cb = 1 / aspect_ratio_cb; 1187734SAli.Saidi@ARM.com 1197734SAli.Saidi@ARM.com if (aspect_ratio_cb < ASPECT_THRESHOLD) { 1207734SAli.Saidi@ARM.com if (n_out > 2 && n_inp > 2) { 1217734SAli.Saidi@ARM.com CB_ADJ += 0.2; 1227734SAli.Saidi@ARM.com //cout << "CB ADJ " << CB_ADJ << endl; 1237734SAli.Saidi@ARM.com if (CB_ADJ < 4) { 1247734SAli.Saidi@ARM.com this->compute_power(); 1256019Shines@cs.fsu.edu } 1266019Shines@cs.fsu.edu } 1276019Shines@cs.fsu.edu } 1286019Shines@cs.fsu.edu 1297697SAli.Saidi@ARM.com 1307404SAli.Saidi@ARM.com 1318527SAli.Saidi@ARM.com power.readOp.dynamic = 1328527SAli.Saidi@ARM.com (w1.power.readOp.dynamic + w2.power.readOp.dynamic + 1336019Shines@cs.fsu.edu (tri_inp_cap * n_out + tri_out_cap * n_inp + tri_ctr_cap + 1346019Shines@cs.fsu.edu tri_int_cap) * Vdd * Vdd) * flit_size; 1356019Shines@cs.fsu.edu power.readOp.leakage = n_inp * n_out * flit_size * ( 1366019Shines@cs.fsu.edu cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS2 * 2, min_w_pmos * TriS2 * 2, 1376019Shines@cs.fsu.edu 1, inv) * Vdd + 1386019Shines@cs.fsu.edu cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 1396019Shines@cs.fsu.edu 2, nand) * Vdd + 1407404SAli.Saidi@ARM.com cmos_Isub_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 1417404SAli.Saidi@ARM.com 2, nor) * Vdd + 1427404SAli.Saidi@ARM.com w1.power.readOp.leakage + w2.power.readOp.leakage); 1436019Shines@cs.fsu.edu power.readOp.gate_leakage = n_inp * n_out * flit_size * ( 1447404SAli.Saidi@ARM.com cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS2 * 2, min_w_pmos * TriS2 * 2, 1457404SAli.Saidi@ARM.com 1, inv) * Vdd + 1467404SAli.Saidi@ARM.com cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 1477404SAli.Saidi@ARM.com 2, nand) * Vdd + 1487404SAli.Saidi@ARM.com cmos_Ig_leakage(g_tp.min_w_nmos_ * TriS1 * 3, min_w_pmos * TriS1 * 3, 1497404SAli.Saidi@ARM.com 2, nor) * Vdd + 1507404SAli.Saidi@ARM.com w1.power.readOp.gate_leakage + w2.power.readOp.gate_leakage); 1517404SAli.Saidi@ARM.com 1527404SAli.Saidi@ARM.com // delay calculation 1537404SAli.Saidi@ARM.com double l_eff = n_inp * flit_size * g_tp.wire_outside_mat.pitch; 1547404SAli.Saidi@ARM.com Wire wdriver(g_ip->wt, l_eff); 1557404SAli.Saidi@ARM.com double res = g_tp.wire_outside_mat.R_per_um * (area.w + area.h) + 1567404SAli.Saidi@ARM.com tr_R_on(g_tp.min_w_nmos_ * wdriver.repeater_size, NCH, 1); 1577404SAli.Saidi@ARM.com double cap = g_tp.wire_outside_mat.C_per_um * (area.w + area.h) + n_out * 1587404SAli.Saidi@ARM.com tri_inp_cap + n_inp * tri_out_cap; 1597404SAli.Saidi@ARM.com delay = horowitz(w1.signal_rise_time(), res * cap, deviceType->Vth / 1607404SAli.Saidi@ARM.com deviceType->Vdd, deviceType->Vth / deviceType->Vdd, RISE); 1617404SAli.Saidi@ARM.com 1627406SAli.Saidi@ARM.com Wire wreset(); 1637406SAli.Saidi@ARM.com} 1647404SAli.Saidi@ARM.com 1657404SAli.Saidi@ARM.comvoid Crossbar::print_crossbar() { 1667404SAli.Saidi@ARM.com cout << "\nCrossbar Stats (" << n_inp << "x" << n_out << ")\n\n"; 1678527SAli.Saidi@ARM.com cout << "Flit size : " << flit_size << " bits" << endl; 1686019Shines@cs.fsu.edu cout << "Width : " << area.w << " u" << endl; 1696019Shines@cs.fsu.edu cout << "Height : " << area.h << " u" << endl; 1707404SAli.Saidi@ARM.com cout << "Dynamic Power : " << power.readOp.dynamic*1e9 * 1716019Shines@cs.fsu.edu MIN(n_inp, n_out) << " (nJ)" << endl; 1726019Shines@cs.fsu.edu cout << "Leakage Power : " << power.readOp.leakage*1e3 << " (mW)" 1736019Shines@cs.fsu.edu << endl; 1746019Shines@cs.fsu.edu cout << "Gate Leakage Power : " << power.readOp.gate_leakage*1e3 1757694SAli.Saidi@ARM.com << " (mW)" << endl; 1767694SAli.Saidi@ARM.com cout << "Crossbar Delay : " << delay*1e12 << " ps\n"; 1777694SAli.Saidi@ARM.com} 1787694SAli.Saidi@ARM.com 1797694SAli.Saidi@ARM.com 1807694SAli.Saidi@ARM.com