cacti_interface.cc revision 10152:52c552138ba1
1/***************************************************************************** 2 * McPAT/CACTI 3 * SOFTWARE LICENSE AGREEMENT 4 * Copyright 2012 Hewlett-Packard Development Company, L.P. 5 * All Rights Reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer; 11 * redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution; 14 * neither the name of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.” 29 * 30 ***************************************************************************/ 31 32#include <pthread.h> 33 34#include <algorithm> 35#include <cmath> 36#include <ctime> 37#include <iostream> 38 39#include "Ucache.h" 40#include "area.h" 41#include "basic_circuit.h" 42#include "cacti_interface.h" 43#include "component.h" 44#include "const.h" 45#include "parameter.h" 46 47using namespace std; 48 49 50bool mem_array::lt(const mem_array * m1, const mem_array * m2) 51{ 52 if (m1->Nspd < m2->Nspd) return true; 53 else if (m1->Nspd > m2->Nspd) return false; 54 else if (m1->Ndwl < m2->Ndwl) return true; 55 else if (m1->Ndwl > m2->Ndwl) return false; 56 else if (m1->Ndbl < m2->Ndbl) return true; 57 else if (m1->Ndbl > m2->Ndbl) return false; 58 else if (m1->deg_bl_muxing < m2->deg_bl_muxing) return true; 59 else if (m1->deg_bl_muxing > m2->deg_bl_muxing) return false; 60 else if (m1->Ndsam_lev_1 < m2->Ndsam_lev_1) return true; 61 else if (m1->Ndsam_lev_1 > m2->Ndsam_lev_1) return false; 62 else if (m1->Ndsam_lev_2 < m2->Ndsam_lev_2) return true; 63 else return false; 64} 65 66 67 68void uca_org_t::find_delay() 69{ 70 mem_array * data_arr = data_array2; 71 mem_array * tag_arr = tag_array2; 72 73 // check whether it is a regular cache or scratch ram 74 if (g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc) 75 { 76 access_time = data_arr->access_time; 77 } 78 // Both tag and data lookup happen in parallel 79 // and the entire set is sent over the data array h-tree without 80 // waiting for the way-select signal --TODO add the corresponding 81 // power overhead Nav 82 else if (g_ip->fast_access == true) 83 { 84 access_time = MAX(tag_arr->access_time, data_arr->access_time); 85 } 86 // Tag is accessed first. On a hit, way-select signal along with the 87 // address is sent to read/write the appropriate block in the data 88 // array 89 else if (g_ip->is_seq_acc == true) 90 { 91 access_time = tag_arr->access_time + data_arr->access_time; 92 } 93 // Normal access: tag array access and data array access happen in parallel. 94 // But, the data array will wait for the way-select and transfer only the 95 // appropriate block over the h-tree. 96 else 97 { 98 access_time = MAX(tag_arr->access_time + data_arr->delay_senseamp_mux_decoder, 99 data_arr->delay_before_subarray_output_driver) + 100 data_arr->delay_from_subarray_output_driver_to_output; 101 } 102} 103 104 105 106void uca_org_t::find_energy() 107{ 108 if (!(g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc))//(g_ip->is_cache) 109 power = data_array2->power + tag_array2->power; 110 else 111 power = data_array2->power; 112} 113 114 115 116void uca_org_t::find_area() 117{ 118 if (g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)//(g_ip->is_cache == false) 119 { 120 cache_ht = data_array2->height; 121 cache_len = data_array2->width; 122 } 123 else 124 { 125 cache_ht = MAX(tag_array2->height, data_array2->height); 126 cache_len = tag_array2->width + data_array2->width; 127 } 128 area = cache_ht * cache_len; 129} 130 131void uca_org_t::adjust_area() 132{ 133 double area_adjust; 134 if (g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc) 135 { 136 if (data_array2->area_efficiency/100.0<0.2) 137 { 138 //area_adjust = sqrt(area/(area*(data_array2->area_efficiency/100.0)/0.2)); 139 area_adjust = sqrt(0.2/(data_array2->area_efficiency/100.0)); 140 cache_ht = cache_ht/area_adjust; 141 cache_len = cache_len/area_adjust; 142 } 143 } 144 area = cache_ht * cache_len; 145} 146 147void uca_org_t::find_cyc() 148{ 149 if ((g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc))//(g_ip->is_cache == false) 150 { 151 cycle_time = data_array2->cycle_time; 152 } 153 else 154 { 155 cycle_time = MAX(tag_array2->cycle_time, 156 data_array2->cycle_time); 157 } 158} 159 160uca_org_t :: uca_org_t() 161:tag_array2(0), 162 data_array2(0) 163{ 164 165} 166 167void uca_org_t :: cleanup() 168{ 169 if (data_array2!=0) 170 delete data_array2; 171 if (tag_array2!=0) 172 delete tag_array2; 173} 174