cacheunit.cc revision 10234
110234Syasuko.eckert@amd.com/***************************************************************************** 210234Syasuko.eckert@amd.com * McPAT 310234Syasuko.eckert@amd.com * SOFTWARE LICENSE AGREEMENT 410234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 510234Syasuko.eckert@amd.com * All Rights Reserved 610234Syasuko.eckert@amd.com * 710234Syasuko.eckert@amd.com * Redistribution and use in source and binary forms, with or without 810234Syasuko.eckert@amd.com * modification, are permitted provided that the following conditions are 910234Syasuko.eckert@amd.com * met: redistributions of source code must retain the above copyright 1010234Syasuko.eckert@amd.com * notice, this list of conditions and the following disclaimer; 1110234Syasuko.eckert@amd.com * redistributions in binary form must reproduce the above copyright 1210234Syasuko.eckert@amd.com * notice, this list of conditions and the following disclaimer in the 1310234Syasuko.eckert@amd.com * documentation and/or other materials provided with the distribution; 1410234Syasuko.eckert@amd.com * neither the name of the copyright holders nor the names of its 1510234Syasuko.eckert@amd.com * contributors may be used to endorse or promote products derived from 1610234Syasuko.eckert@amd.com * this software without specific prior written permission. 1710234Syasuko.eckert@amd.com 1810234Syasuko.eckert@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1910234Syasuko.eckert@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2010234Syasuko.eckert@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2110234Syasuko.eckert@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2210234Syasuko.eckert@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2310234Syasuko.eckert@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2410234Syasuko.eckert@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2510234Syasuko.eckert@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2610234Syasuko.eckert@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2710234Syasuko.eckert@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2810234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2910234Syasuko.eckert@amd.com * 3010234Syasuko.eckert@amd.com * Authors: Joel Hestness 3110234Syasuko.eckert@amd.com * Yasuko Eckert 3210234Syasuko.eckert@amd.com * 3310234Syasuko.eckert@amd.com ***************************************************************************/ 3410234Syasuko.eckert@amd.com 3510234Syasuko.eckert@amd.com#include <algorithm> 3610234Syasuko.eckert@amd.com#include <cmath> 3710234Syasuko.eckert@amd.com#include <cstring> 3810234Syasuko.eckert@amd.com#include <iostream> 3910234Syasuko.eckert@amd.com 4010234Syasuko.eckert@amd.com#include "arbiter.h" 4110234Syasuko.eckert@amd.com#include "array.h" 4210234Syasuko.eckert@amd.com#include "basic_circuit.h" 4310234Syasuko.eckert@amd.com#include "cachearray.h" 4410234Syasuko.eckert@amd.com#include "cacheunit.h" 4510234Syasuko.eckert@amd.com#include "common.h" 4610234Syasuko.eckert@amd.com#include "const.h" 4710234Syasuko.eckert@amd.com#include "io.h" 4810234Syasuko.eckert@amd.com#include "logic.h" 4910234Syasuko.eckert@amd.com#include "parameter.h" 5010234Syasuko.eckert@amd.com 5110234Syasuko.eckert@amd.combool CacheUnit::is_cache = true; 5210234Syasuko.eckert@amd.combool CacheUnit::pure_cam = false; 5310234Syasuko.eckert@amd.combool CacheUnit::opt_local = true; 5410234Syasuko.eckert@amd.combool CacheUnit::force_cache_config = false; 5510234Syasuko.eckert@amd.com 5610234Syasuko.eckert@amd.comCacheUnit::CacheUnit(XMLNode* _xml_data, InputParameter* _interface_ip) 5710234Syasuko.eckert@amd.com : dir_overhead(0), McPATComponent(_xml_data, _interface_ip) { 5810234Syasuko.eckert@amd.com 5910234Syasuko.eckert@amd.com int tag; 6010234Syasuko.eckert@amd.com int data; 6110234Syasuko.eckert@amd.com 6210234Syasuko.eckert@amd.com name = "Cache Unit"; 6310234Syasuko.eckert@amd.com CacheArray* arrayPtr = NULL; 6410234Syasuko.eckert@amd.com 6510234Syasuko.eckert@amd.com set_cache_param_from_xml_data(); 6610234Syasuko.eckert@amd.com 6710234Syasuko.eckert@amd.com //All lower level cache are physically indexed and tagged. 6810234Syasuko.eckert@amd.com double size; 6910234Syasuko.eckert@amd.com double line; 7010234Syasuko.eckert@amd.com double assoc; 7110234Syasuko.eckert@amd.com double banks; 7210234Syasuko.eckert@amd.com size = cache_params.capacity; 7310234Syasuko.eckert@amd.com line = cache_params.blockW; 7410234Syasuko.eckert@amd.com assoc = cache_params.assoc; 7510234Syasuko.eckert@amd.com banks = cache_params.nbanks; 7610234Syasuko.eckert@amd.com if ((cache_params.dir_ty == ST && 7710234Syasuko.eckert@amd.com cache_params.cache_level == L1Directory) || 7810234Syasuko.eckert@amd.com (cache_params.dir_ty == ST && 7910234Syasuko.eckert@amd.com cache_params.cache_level == L2Directory)) { 8010234Syasuko.eckert@amd.com tag = physical_address_width + EXTRA_TAG_BITS; 8110234Syasuko.eckert@amd.com } else { 8210234Syasuko.eckert@amd.com tag = physical_address_width - int(ceil(log2(size / line / assoc))) - 8310234Syasuko.eckert@amd.com int(ceil(log2(line))) + EXTRA_TAG_BITS; 8410234Syasuko.eckert@amd.com 8510234Syasuko.eckert@amd.com if (cache_params.dir_ty == SBT) { 8610234Syasuko.eckert@amd.com dir_overhead = ceil(cache_params.num_cores / BITS_PER_BYTE) * 8710234Syasuko.eckert@amd.com BITS_PER_BYTE / (line * BITS_PER_BYTE); 8810234Syasuko.eckert@amd.com line *= (1 + dir_overhead); 8910234Syasuko.eckert@amd.com size *= (1 + dir_overhead); 9010234Syasuko.eckert@amd.com } 9110234Syasuko.eckert@amd.com } 9210234Syasuko.eckert@amd.com 9310234Syasuko.eckert@amd.com interface_ip.cache_sz = (int)size; 9410234Syasuko.eckert@amd.com interface_ip.line_sz = (int)line; 9510234Syasuko.eckert@amd.com interface_ip.assoc = (int)assoc; 9610234Syasuko.eckert@amd.com interface_ip.nbanks = (int)banks; 9710234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 9810234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 9910234Syasuko.eckert@amd.com 10010234Syasuko.eckert@amd.com if (cache_params.cache_level == L1) { 10110234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 10210234Syasuko.eckert@amd.com } else { 10310234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE / 2; 10410234Syasuko.eckert@amd.com } 10510234Syasuko.eckert@amd.com 10610234Syasuko.eckert@amd.com interface_ip.access_mode = cache_params.cache_access_mode; 10710234Syasuko.eckert@amd.com interface_ip.throughput= cache_params.throughput; 10810234Syasuko.eckert@amd.com interface_ip.latency = cache_params.latency; 10910234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 11010234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 11110234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 11210234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 11310234Syasuko.eckert@amd.com interface_ip.is_cache = is_cache; 11410234Syasuko.eckert@amd.com interface_ip.pure_ram = cache_params.pure_ram; 11510234Syasuko.eckert@amd.com interface_ip.pure_cam = pure_cam; 11610234Syasuko.eckert@amd.com interface_ip.num_rw_ports = cache_params.cache_rw_ports; 11710234Syasuko.eckert@amd.com interface_ip.num_rd_ports = cache_params.cache_rd_ports; 11810234Syasuko.eckert@amd.com interface_ip.num_wr_ports = cache_params.cache_wr_ports; 11910234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = cache_params.cache_se_rd_ports; 12010234Syasuko.eckert@amd.com interface_ip.num_search_ports = cache_params.cache_search_ports; 12110234Syasuko.eckert@amd.com 12210234Syasuko.eckert@amd.com arrayPtr = new CacheArray(xml_data, &interface_ip, "Data and Tag Arrays", 12310234Syasuko.eckert@amd.com cache_params.device_ty, clockRate, opt_local, 12410234Syasuko.eckert@amd.com cache_params.core_ty); 12510234Syasuko.eckert@amd.com children.push_back(arrayPtr); 12610234Syasuko.eckert@amd.com 12710234Syasuko.eckert@amd.com // This is for calculating TDP, which depends on the number of 12810234Syasuko.eckert@amd.com // available ports 12910234Syasuko.eckert@amd.com int num_tdp_ports = arrayPtr->l_ip.num_rw_ports + 13010234Syasuko.eckert@amd.com arrayPtr->l_ip.num_rd_ports + arrayPtr->l_ip.num_wr_ports; 13110234Syasuko.eckert@amd.com 13210234Syasuko.eckert@amd.com // Set new array stats for calculating TDP and runtime power 13310234Syasuko.eckert@amd.com arrayPtr->tdp_stats.reset(); 13410234Syasuko.eckert@amd.com arrayPtr->tdp_stats.readAc.access = cache_stats.tdp_read_access_scalar * 13510234Syasuko.eckert@amd.com num_tdp_ports * cache_stats.duty_cycle * 13610234Syasuko.eckert@amd.com cache_stats.homenode_access_scalar; 13710234Syasuko.eckert@amd.com arrayPtr->tdp_stats.readAc.miss = 0; 13810234Syasuko.eckert@amd.com arrayPtr->tdp_stats.readAc.hit = arrayPtr->tdp_stats.readAc.access - 13910234Syasuko.eckert@amd.com arrayPtr->tdp_stats.readAc.miss; 14010234Syasuko.eckert@amd.com arrayPtr->tdp_stats.writeAc.access = cache_stats.tdp_write_access_scalar * 14110234Syasuko.eckert@amd.com num_tdp_ports * cache_stats.duty_cycle * 14210234Syasuko.eckert@amd.com cache_stats.homenode_access_scalar; 14310234Syasuko.eckert@amd.com arrayPtr->tdp_stats.writeAc.miss = 0; 14410234Syasuko.eckert@amd.com arrayPtr->tdp_stats.writeAc.hit = arrayPtr->tdp_stats.writeAc.access - 14510234Syasuko.eckert@amd.com arrayPtr->tdp_stats.writeAc.miss; 14610234Syasuko.eckert@amd.com arrayPtr->tdp_stats.searchAc.access = 0; 14710234Syasuko.eckert@amd.com arrayPtr->tdp_stats.searchAc.miss = 0; 14810234Syasuko.eckert@amd.com arrayPtr->tdp_stats.searchAc.hit = 0; 14910234Syasuko.eckert@amd.com 15010234Syasuko.eckert@amd.com arrayPtr->rtp_stats.reset(); 15110234Syasuko.eckert@amd.com if (cache_stats.use_detailed_stats) { 15210234Syasuko.eckert@amd.com arrayPtr->rtp_stats.dataReadAc.access = 15310234Syasuko.eckert@amd.com cache_stats.num_data_array_reads; 15410234Syasuko.eckert@amd.com arrayPtr->rtp_stats.dataWriteAc.access = 15510234Syasuko.eckert@amd.com cache_stats.num_data_array_writes; 15610234Syasuko.eckert@amd.com arrayPtr->rtp_stats.tagReadAc.access = 15710234Syasuko.eckert@amd.com cache_stats.num_tag_array_reads; 15810234Syasuko.eckert@amd.com arrayPtr->rtp_stats.tagWriteAc.access = 15910234Syasuko.eckert@amd.com cache_stats.num_tag_array_writes; 16010234Syasuko.eckert@amd.com } else { 16110234Syasuko.eckert@amd.com // This code makes assumptions. For instance, it assumes that 16210234Syasuko.eckert@amd.com // tag and data arrays are accessed in parallel on a read request and 16310234Syasuko.eckert@amd.com // this is a write-allocate cache. It also ignores any coherence 16410234Syasuko.eckert@amd.com // requests. Using detailed stats as above can avoid the ambiguity 16510234Syasuko.eckert@amd.com // that is introduced here 16610234Syasuko.eckert@amd.com arrayPtr->rtp_stats.dataReadAc.access = 16710234Syasuko.eckert@amd.com cache_stats.read_accesses + cache_stats.write_misses; 16810234Syasuko.eckert@amd.com arrayPtr->rtp_stats.dataWriteAc.access = 16910234Syasuko.eckert@amd.com cache_stats.write_accesses + cache_stats.read_misses; 17010234Syasuko.eckert@amd.com arrayPtr->rtp_stats.tagReadAc.access = 17110234Syasuko.eckert@amd.com cache_stats.read_accesses + cache_stats.write_accesses; 17210234Syasuko.eckert@amd.com arrayPtr->rtp_stats.tagWriteAc.access = 17310234Syasuko.eckert@amd.com cache_stats.read_misses + cache_stats.write_misses; 17410234Syasuko.eckert@amd.com } 17510234Syasuko.eckert@amd.com 17610234Syasuko.eckert@amd.com // Set SBT stats if this is an SBT directory type 17710234Syasuko.eckert@amd.com if (dir_overhead > 0) { 17810234Syasuko.eckert@amd.com arrayPtr->setSBTDirOverhead(dir_overhead); 17910234Syasuko.eckert@amd.com 18010234Syasuko.eckert@amd.com // TDP stats 18110234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.readAc.access = 18210234Syasuko.eckert@amd.com cache_stats.tdp_read_access_scalar * 18310234Syasuko.eckert@amd.com num_tdp_ports * cache_stats.dir_duty_cycle * 18410234Syasuko.eckert@amd.com (1 - cache_stats.homenode_access_scalar); 18510234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.readAc.miss = 0; 18610234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.readAc.hit = 18710234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.readAc.access - 18810234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.readAc.miss; 18910234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.writeAc.access = 19010234Syasuko.eckert@amd.com cache_stats.tdp_sbt_write_access_scalar * 19110234Syasuko.eckert@amd.com num_tdp_ports * cache_stats.dir_duty_cycle * 19210234Syasuko.eckert@amd.com (1 - cache_stats.homenode_access_scalar); 19310234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.writeAc.miss = 0; 19410234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.writeAc.hit = 19510234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.writeAc.access - 19610234Syasuko.eckert@amd.com arrayPtr->sbt_tdp_stats.writeAc.miss; 19710234Syasuko.eckert@amd.com 19810234Syasuko.eckert@amd.com // Runtime power stats 19910234Syasuko.eckert@amd.com arrayPtr->sbt_rtp_stats.readAc.access = 20010234Syasuko.eckert@amd.com cache_stats.homenode_read_accesses; 20110234Syasuko.eckert@amd.com arrayPtr->sbt_rtp_stats.readAc.miss = 20210234Syasuko.eckert@amd.com cache_stats.homenode_read_misses; 20310234Syasuko.eckert@amd.com arrayPtr->sbt_rtp_stats.readAc.access = 20410234Syasuko.eckert@amd.com cache_stats.homenode_read_accesses - 20510234Syasuko.eckert@amd.com cache_stats.homenode_read_misses; 20610234Syasuko.eckert@amd.com arrayPtr->sbt_rtp_stats.writeAc.access = 20710234Syasuko.eckert@amd.com cache_stats.homenode_write_accesses; 20810234Syasuko.eckert@amd.com arrayPtr->sbt_rtp_stats.writeAc.miss = 20910234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 21010234Syasuko.eckert@amd.com arrayPtr->sbt_rtp_stats.writeAc.hit = 21110234Syasuko.eckert@amd.com cache_stats.homenode_write_accesses - 21210234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 21310234Syasuko.eckert@amd.com } 21410234Syasuko.eckert@amd.com 21510234Syasuko.eckert@amd.com interface_ip.force_cache_config = force_cache_config; 21610234Syasuko.eckert@amd.com if (!((cache_params.dir_ty == ST && 21710234Syasuko.eckert@amd.com cache_params.cache_level == L1Directory) || 21810234Syasuko.eckert@amd.com (cache_params.dir_ty == ST && 21910234Syasuko.eckert@amd.com cache_params.cache_level== L2Directory))) { 22010234Syasuko.eckert@amd.com // Miss Buffer 22110234Syasuko.eckert@amd.com tag = physical_address_width + EXTRA_TAG_BITS; 22210234Syasuko.eckert@amd.com data = (physical_address_width) + 22310234Syasuko.eckert@amd.com int(ceil(log2(size / cache_params.blockW))) + 22410234Syasuko.eckert@amd.com (cache_params.blockW * BITS_PER_BYTE); 22510234Syasuko.eckert@amd.com line = int(ceil(data / BITS_PER_BYTE)); 22610234Syasuko.eckert@amd.com size = cache_params.missb_size * line; 22710234Syasuko.eckert@amd.com 22810234Syasuko.eckert@amd.com interface_ip.cache_sz = size; 22910234Syasuko.eckert@amd.com interface_ip.line_sz = line; 23010234Syasuko.eckert@amd.com interface_ip.assoc = cache_params.missb_assoc; 23110234Syasuko.eckert@amd.com interface_ip.nbanks = cache_params.missb_banks; 23210234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 23310234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 23410234Syasuko.eckert@amd.com 23510234Syasuko.eckert@amd.com if (cache_params.cache_level == L1) { 23610234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE; 23710234Syasuko.eckert@amd.com } else { 23810234Syasuko.eckert@amd.com interface_ip.out_w = line * BITS_PER_BYTE / 2; 23910234Syasuko.eckert@amd.com } 24010234Syasuko.eckert@amd.com 24110234Syasuko.eckert@amd.com interface_ip.access_mode = cache_params.miss_buff_access_mode; 24210234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 24310234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 24410234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 24510234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 24610234Syasuko.eckert@amd.com interface_ip.is_cache = is_cache; 24710234Syasuko.eckert@amd.com interface_ip.pure_ram = cache_params.pure_ram; 24810234Syasuko.eckert@amd.com interface_ip.pure_cam = pure_cam; 24910234Syasuko.eckert@amd.com interface_ip.throughput = cache_params.throughput; 25010234Syasuko.eckert@amd.com interface_ip.latency = cache_params.latency; 25110234Syasuko.eckert@amd.com interface_ip.num_rw_ports = cache_params.miss_buff_rw_ports; 25210234Syasuko.eckert@amd.com interface_ip.num_rd_ports = cache_params.miss_buff_rd_ports; 25310234Syasuko.eckert@amd.com interface_ip.num_wr_ports = cache_params.miss_buff_wr_ports; 25410234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = cache_params.miss_buff_se_rd_ports; 25510234Syasuko.eckert@amd.com interface_ip.num_search_ports = cache_params.miss_buff_search_ports; 25610234Syasuko.eckert@amd.com 25710234Syasuko.eckert@amd.com arrayPtr = new CacheArray(xml_data, &interface_ip, "Miss Buffer", 25810234Syasuko.eckert@amd.com cache_params.device_ty, clockRate, opt_local, 25910234Syasuko.eckert@amd.com cache_params.core_ty); 26010234Syasuko.eckert@amd.com children.push_back(arrayPtr); 26110234Syasuko.eckert@amd.com 26210234Syasuko.eckert@amd.com arrayPtr->tdp_stats.reset(); 26310234Syasuko.eckert@amd.com arrayPtr->tdp_stats.readAc.access = 0; 26410234Syasuko.eckert@amd.com arrayPtr->tdp_stats.writeAc.access = arrayPtr->l_ip.num_search_ports; 26510234Syasuko.eckert@amd.com arrayPtr->tdp_stats.searchAc.access = arrayPtr->l_ip.num_search_ports; 26610234Syasuko.eckert@amd.com 26710234Syasuko.eckert@amd.com arrayPtr->rtp_stats.reset(); 26810234Syasuko.eckert@amd.com arrayPtr->rtp_stats.readAc.access = 26910234Syasuko.eckert@amd.com cache_stats.read_misses + cache_stats.write_misses; 27010234Syasuko.eckert@amd.com arrayPtr->rtp_stats.writeAc.access = 27110234Syasuko.eckert@amd.com cache_stats.read_misses + cache_stats.write_misses; 27210234Syasuko.eckert@amd.com arrayPtr->rtp_stats.searchAc.access = 0; 27310234Syasuko.eckert@amd.com 27410234Syasuko.eckert@amd.com if (cache_params.dir_ty == SBT) { 27510234Syasuko.eckert@amd.com arrayPtr->rtp_stats.readAc.access += 27610234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 27710234Syasuko.eckert@amd.com arrayPtr->rtp_stats.writeAc.access += 27810234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 27910234Syasuko.eckert@amd.com } 28010234Syasuko.eckert@amd.com 28110234Syasuko.eckert@amd.com // Fill Buffer 28210234Syasuko.eckert@amd.com tag = physical_address_width + EXTRA_TAG_BITS; 28310234Syasuko.eckert@amd.com data = cache_params.blockW; 28410234Syasuko.eckert@amd.com 28510234Syasuko.eckert@amd.com interface_ip.cache_sz = data * cache_params.fu_size; 28610234Syasuko.eckert@amd.com interface_ip.line_sz = data; 28710234Syasuko.eckert@amd.com interface_ip.assoc = cache_params.fu_assoc; 28810234Syasuko.eckert@amd.com interface_ip.nbanks = cache_params.fu_banks; 28910234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 29010234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 29110234Syasuko.eckert@amd.com 29210234Syasuko.eckert@amd.com if (cache_params.cache_level == L1) { 29310234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 29410234Syasuko.eckert@amd.com } else { 29510234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE / 2; 29610234Syasuko.eckert@amd.com } 29710234Syasuko.eckert@amd.com 29810234Syasuko.eckert@amd.com interface_ip.access_mode = cache_params.fetch_buff_access_mode; 29910234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 30010234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 30110234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 30210234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 30310234Syasuko.eckert@amd.com interface_ip.is_cache = is_cache; 30410234Syasuko.eckert@amd.com interface_ip.pure_cam = pure_cam; 30510234Syasuko.eckert@amd.com interface_ip.throughput = cache_params.throughput; 30610234Syasuko.eckert@amd.com interface_ip.latency = cache_params.latency; 30710234Syasuko.eckert@amd.com interface_ip.num_rw_ports = cache_params.fetch_buff_rw_ports; 30810234Syasuko.eckert@amd.com interface_ip.num_rd_ports = cache_params.fetch_buff_rd_ports; 30910234Syasuko.eckert@amd.com interface_ip.num_wr_ports = cache_params.fetch_buff_wr_ports; 31010234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = cache_params.fetch_buff_se_rd_ports; 31110234Syasuko.eckert@amd.com interface_ip.num_search_ports = cache_params.fetch_buff_search_ports; 31210234Syasuko.eckert@amd.com arrayPtr = new CacheArray(xml_data, &interface_ip, "Fill Buffer", 31310234Syasuko.eckert@amd.com cache_params.device_ty, clockRate, opt_local, 31410234Syasuko.eckert@amd.com cache_params.core_ty); 31510234Syasuko.eckert@amd.com children.push_back(arrayPtr); 31610234Syasuko.eckert@amd.com 31710234Syasuko.eckert@amd.com arrayPtr->tdp_stats.reset(); 31810234Syasuko.eckert@amd.com arrayPtr->tdp_stats.readAc.access = 0; 31910234Syasuko.eckert@amd.com arrayPtr->tdp_stats.writeAc.access = arrayPtr->l_ip.num_search_ports; 32010234Syasuko.eckert@amd.com arrayPtr->tdp_stats.searchAc.access = arrayPtr->l_ip.num_search_ports; 32110234Syasuko.eckert@amd.com 32210234Syasuko.eckert@amd.com arrayPtr->rtp_stats.reset(); 32310234Syasuko.eckert@amd.com arrayPtr->rtp_stats.readAc.access = 32410234Syasuko.eckert@amd.com cache_stats.read_misses + cache_stats.write_misses; 32510234Syasuko.eckert@amd.com arrayPtr->rtp_stats.writeAc.access = 32610234Syasuko.eckert@amd.com cache_stats.read_misses + cache_stats.write_misses; 32710234Syasuko.eckert@amd.com arrayPtr->rtp_stats.searchAc.access = 0; 32810234Syasuko.eckert@amd.com 32910234Syasuko.eckert@amd.com if (cache_params.dir_ty == SBT) { 33010234Syasuko.eckert@amd.com arrayPtr->rtp_stats.readAc.access += 33110234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 33210234Syasuko.eckert@amd.com arrayPtr->rtp_stats.writeAc.access += 33310234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 33410234Syasuko.eckert@amd.com } 33510234Syasuko.eckert@amd.com 33610234Syasuko.eckert@amd.com // Prefetch Buffer 33710234Syasuko.eckert@amd.com tag = physical_address_width + EXTRA_TAG_BITS; 33810234Syasuko.eckert@amd.com line = cache_params.blockW; 33910234Syasuko.eckert@amd.com 34010234Syasuko.eckert@amd.com interface_ip.cache_sz = cache_params.prefetchb_size * line; 34110234Syasuko.eckert@amd.com interface_ip.line_sz = line; 34210234Syasuko.eckert@amd.com interface_ip.assoc = cache_params.prefetchb_assoc; 34310234Syasuko.eckert@amd.com interface_ip.nbanks = cache_params.prefetchb_banks; 34410234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 34510234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 34610234Syasuko.eckert@amd.com 34710234Syasuko.eckert@amd.com if (cache_params.cache_level == L1) { 34810234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 34910234Syasuko.eckert@amd.com } else { 35010234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE / 2; 35110234Syasuko.eckert@amd.com } 35210234Syasuko.eckert@amd.com 35310234Syasuko.eckert@amd.com interface_ip.access_mode = cache_params.prefetch_buff_access_mode; 35410234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 35510234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 35610234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 35710234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 35810234Syasuko.eckert@amd.com interface_ip.is_cache = is_cache; 35910234Syasuko.eckert@amd.com interface_ip.pure_ram = cache_params.pure_ram; 36010234Syasuko.eckert@amd.com interface_ip.pure_cam = pure_cam; 36110234Syasuko.eckert@amd.com interface_ip.throughput = cache_params.throughput; 36210234Syasuko.eckert@amd.com interface_ip.latency = cache_params.latency; 36310234Syasuko.eckert@amd.com interface_ip.num_rw_ports = cache_params.pf_buff_rw_ports; 36410234Syasuko.eckert@amd.com interface_ip.num_rd_ports = cache_params.pf_buff_rd_ports; 36510234Syasuko.eckert@amd.com interface_ip.num_wr_ports = cache_params.pf_buff_wr_ports; 36610234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = cache_params.pf_buff_se_rd_ports; 36710234Syasuko.eckert@amd.com interface_ip.num_search_ports = cache_params.pf_buff_search_ports; 36810234Syasuko.eckert@amd.com arrayPtr = new CacheArray(xml_data, &interface_ip, "Prefetch Buffer", 36910234Syasuko.eckert@amd.com cache_params.device_ty, clockRate, opt_local, 37010234Syasuko.eckert@amd.com cache_params.core_ty); 37110234Syasuko.eckert@amd.com children.push_back(arrayPtr); 37210234Syasuko.eckert@amd.com 37310234Syasuko.eckert@amd.com arrayPtr->tdp_stats.reset(); 37410234Syasuko.eckert@amd.com arrayPtr->tdp_stats.readAc.access = 0; 37510234Syasuko.eckert@amd.com arrayPtr->tdp_stats.writeAc.access = arrayPtr->l_ip.num_search_ports; 37610234Syasuko.eckert@amd.com arrayPtr->tdp_stats.searchAc.access = arrayPtr->l_ip.num_search_ports; 37710234Syasuko.eckert@amd.com 37810234Syasuko.eckert@amd.com arrayPtr->rtp_stats.reset(); 37910234Syasuko.eckert@amd.com arrayPtr->rtp_stats.readAc.access = cache_stats.read_misses; 38010234Syasuko.eckert@amd.com arrayPtr->rtp_stats.writeAc.access = cache_stats.read_misses; 38110234Syasuko.eckert@amd.com arrayPtr->rtp_stats.searchAc.access = 0; 38210234Syasuko.eckert@amd.com 38310234Syasuko.eckert@amd.com if (cache_params.dir_ty == SBT) { 38410234Syasuko.eckert@amd.com arrayPtr->rtp_stats.readAc.access += 38510234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 38610234Syasuko.eckert@amd.com arrayPtr->rtp_stats.writeAc.access += 38710234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 38810234Syasuko.eckert@amd.com } 38910234Syasuko.eckert@amd.com 39010234Syasuko.eckert@amd.com // Writeback Buffer 39110234Syasuko.eckert@amd.com if (cache_params.wbb_size > 0) { 39210234Syasuko.eckert@amd.com tag = physical_address_width + EXTRA_TAG_BITS; 39310234Syasuko.eckert@amd.com line = cache_params.blockW; 39410234Syasuko.eckert@amd.com 39510234Syasuko.eckert@amd.com interface_ip.cache_sz = cache_params.wbb_size * line; 39610234Syasuko.eckert@amd.com interface_ip.line_sz = line; 39710234Syasuko.eckert@amd.com interface_ip.assoc = cache_params.wbb_assoc; 39810234Syasuko.eckert@amd.com interface_ip.nbanks = cache_params.wbb_banks; 39910234Syasuko.eckert@amd.com interface_ip.specific_tag = tag > 0; 40010234Syasuko.eckert@amd.com interface_ip.tag_w = tag; 40110234Syasuko.eckert@amd.com 40210234Syasuko.eckert@amd.com if (cache_params.cache_level == L1) { 40310234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE; 40410234Syasuko.eckert@amd.com } else { 40510234Syasuko.eckert@amd.com interface_ip.out_w = interface_ip.line_sz * BITS_PER_BYTE / 2; 40610234Syasuko.eckert@amd.com } 40710234Syasuko.eckert@amd.com 40810234Syasuko.eckert@amd.com interface_ip.access_mode = cache_params.writeback_buff_access_mode; 40910234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_energy = 0; 41010234Syasuko.eckert@amd.com interface_ip.obj_func_dyn_power = 0; 41110234Syasuko.eckert@amd.com interface_ip.obj_func_leak_power = 0; 41210234Syasuko.eckert@amd.com interface_ip.obj_func_cycle_t = 1; 41310234Syasuko.eckert@amd.com interface_ip.is_cache = is_cache; 41410234Syasuko.eckert@amd.com interface_ip.pure_ram = cache_params.pure_ram; 41510234Syasuko.eckert@amd.com interface_ip.pure_cam = pure_cam; 41610234Syasuko.eckert@amd.com interface_ip.throughput = cache_params.throughput; 41710234Syasuko.eckert@amd.com interface_ip.latency = cache_params.latency; 41810234Syasuko.eckert@amd.com interface_ip.num_rw_ports = cache_params.wb_buff_rw_ports; 41910234Syasuko.eckert@amd.com interface_ip.num_rd_ports = cache_params.wb_buff_rd_ports; 42010234Syasuko.eckert@amd.com interface_ip.num_wr_ports = cache_params.wb_buff_wr_ports; 42110234Syasuko.eckert@amd.com interface_ip.num_se_rd_ports = cache_params.wb_buff_se_rd_ports; 42210234Syasuko.eckert@amd.com interface_ip.num_search_ports = cache_params.wb_buff_search_ports; 42310234Syasuko.eckert@amd.com arrayPtr = new CacheArray(xml_data, &interface_ip, 42410234Syasuko.eckert@amd.com "Writeback Buffer", 42510234Syasuko.eckert@amd.com cache_params.device_ty, clockRate, 42610234Syasuko.eckert@amd.com opt_local, cache_params.core_ty); 42710234Syasuko.eckert@amd.com children.push_back(arrayPtr); 42810234Syasuko.eckert@amd.com 42910234Syasuko.eckert@amd.com arrayPtr->tdp_stats.reset(); 43010234Syasuko.eckert@amd.com arrayPtr->tdp_stats.readAc.access = 0; 43110234Syasuko.eckert@amd.com arrayPtr->tdp_stats.writeAc.access = 43210234Syasuko.eckert@amd.com arrayPtr->l_ip.num_search_ports; 43310234Syasuko.eckert@amd.com arrayPtr->tdp_stats.searchAc.access = 43410234Syasuko.eckert@amd.com arrayPtr->l_ip.num_search_ports; 43510234Syasuko.eckert@amd.com 43610234Syasuko.eckert@amd.com arrayPtr->rtp_stats.reset(); 43710234Syasuko.eckert@amd.com arrayPtr->rtp_stats.readAc.access = cache_stats.write_misses; 43810234Syasuko.eckert@amd.com arrayPtr->rtp_stats.writeAc.access = cache_stats.write_misses; 43910234Syasuko.eckert@amd.com arrayPtr->rtp_stats.searchAc.access = 0; 44010234Syasuko.eckert@amd.com 44110234Syasuko.eckert@amd.com if (cache_params.dir_ty == SBT) { 44210234Syasuko.eckert@amd.com arrayPtr->rtp_stats.readAc.access += 44310234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 44410234Syasuko.eckert@amd.com arrayPtr->rtp_stats.writeAc.access += 44510234Syasuko.eckert@amd.com cache_stats.homenode_write_misses; 44610234Syasuko.eckert@amd.com } 44710234Syasuko.eckert@amd.com } 44810234Syasuko.eckert@amd.com } 44910234Syasuko.eckert@amd.com} 45010234Syasuko.eckert@amd.com 45110234Syasuko.eckert@amd.comvoid CacheUnit::computeEnergy() { 45210234Syasuko.eckert@amd.com McPATComponent::computeEnergy(); 45310234Syasuko.eckert@amd.com} 45410234Syasuko.eckert@amd.com 45510234Syasuko.eckert@amd.comvoid CacheUnit::set_cache_param_from_xml_data() { 45610234Syasuko.eckert@amd.com int level, type; 45710234Syasuko.eckert@amd.com 45810234Syasuko.eckert@amd.com // Initialization... move this? 45910234Syasuko.eckert@amd.com memset(&cache_params, 0, sizeof(CacheParameters)); 46010234Syasuko.eckert@amd.com memset(&cache_stats, 0, sizeof(CacheStatistics)); 46110234Syasuko.eckert@amd.com 46210234Syasuko.eckert@amd.com // By default, use the core clock frequency. This can be changed by 46310234Syasuko.eckert@amd.com // setting the clockrate param in the XML definition of the CacheUnit 46410234Syasuko.eckert@amd.com clockRate = target_core_clockrate; 46510234Syasuko.eckert@amd.com XMLCSTR comp_name = xml_data->getAttribute("name"); 46610234Syasuko.eckert@amd.com if (comp_name) { 46710234Syasuko.eckert@amd.com name = comp_name; 46810234Syasuko.eckert@amd.com } 46910234Syasuko.eckert@amd.com 47010234Syasuko.eckert@amd.com int num_children = xml_data->nChildNode("param"); 47110234Syasuko.eckert@amd.com int i; 47210234Syasuko.eckert@amd.com int tech_type; 47310234Syasuko.eckert@amd.com int mat_type; 47410234Syasuko.eckert@amd.com for (i = 0; i < num_children; i++) { 47510234Syasuko.eckert@amd.com XMLNode* paramNode = xml_data->getChildNodePtr("param", &i); 47610234Syasuko.eckert@amd.com XMLCSTR node_name = paramNode->getAttribute("name"); 47710234Syasuko.eckert@amd.com XMLCSTR value = paramNode->getAttribute("value"); 47810234Syasuko.eckert@amd.com 47910234Syasuko.eckert@amd.com if (!node_name) 48010234Syasuko.eckert@amd.com warnMissingParamName(paramNode->getAttribute("id")); 48110234Syasuko.eckert@amd.com 48210234Syasuko.eckert@amd.com ASSIGN_INT_IF("level", level); 48310234Syasuko.eckert@amd.com ASSIGN_FP_IF("size", cache_params.capacity); 48410234Syasuko.eckert@amd.com ASSIGN_FP_IF("block_size", cache_params.blockW); 48510234Syasuko.eckert@amd.com ASSIGN_FP_IF("assoc", cache_params.assoc); 48610234Syasuko.eckert@amd.com ASSIGN_FP_IF("num_banks", cache_params.nbanks); 48710234Syasuko.eckert@amd.com ASSIGN_FP_IF("latency", cache_params.latency); 48810234Syasuko.eckert@amd.com ASSIGN_FP_IF("throughput", cache_params.throughput); 48910234Syasuko.eckert@amd.com ASSIGN_INT_IF("miss_buffer_size", cache_params.missb_size); 49010234Syasuko.eckert@amd.com ASSIGN_INT_IF("fetch_buffer_size", cache_params.fu_size); 49110234Syasuko.eckert@amd.com ASSIGN_INT_IF("prefetch_buffer_size", cache_params.prefetchb_size); 49210234Syasuko.eckert@amd.com ASSIGN_INT_IF("writeback_buffer_size", cache_params.wbb_size); 49310234Syasuko.eckert@amd.com ASSIGN_INT_IF("miss_buffer_assoc", cache_params.missb_assoc); 49410234Syasuko.eckert@amd.com ASSIGN_INT_IF("fetch_buffer_assoc", cache_params.fu_assoc); 49510234Syasuko.eckert@amd.com ASSIGN_INT_IF("prefetch_buffer_assoc", cache_params.prefetchb_assoc); 49610234Syasuko.eckert@amd.com ASSIGN_INT_IF("writeback_buffer_assoc", cache_params.wbb_assoc); 49710234Syasuko.eckert@amd.com ASSIGN_INT_IF("miss_buffer_banks", cache_params.missb_banks); 49810234Syasuko.eckert@amd.com ASSIGN_INT_IF("fetch_buffer_banks", cache_params.fu_banks); 49910234Syasuko.eckert@amd.com ASSIGN_INT_IF("prefetch_buffer_banks", cache_params.prefetchb_banks); 50010234Syasuko.eckert@amd.com ASSIGN_INT_IF("writeback_buffer_banks", cache_params.wbb_banks); 50110234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("cache_access_mode", 50210234Syasuko.eckert@amd.com cache_params.cache_access_mode, Access_mode); 50310234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("miss_buff_access_mode", 50410234Syasuko.eckert@amd.com cache_params.miss_buff_access_mode, Access_mode); 50510234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("fetch_buff_access_mode", 50610234Syasuko.eckert@amd.com cache_params.fetch_buff_access_mode, Access_mode); 50710234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("prefetch_buff_access_mode", 50810234Syasuko.eckert@amd.com cache_params.prefetch_buff_access_mode, Access_mode); 50910234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("writeback_buff_access_mode", 51010234Syasuko.eckert@amd.com cache_params.writeback_buff_access_mode, Access_mode); 51110234Syasuko.eckert@amd.com ASSIGN_INT_IF("cache_rw_ports", cache_params.cache_rw_ports); 51210234Syasuko.eckert@amd.com ASSIGN_INT_IF("cache_rd_ports", cache_params.cache_rd_ports); 51310234Syasuko.eckert@amd.com ASSIGN_INT_IF("cache_wr_ports", cache_params.cache_wr_ports); 51410234Syasuko.eckert@amd.com ASSIGN_INT_IF("cache_se_rd_ports", cache_params.cache_se_rd_ports); 51510234Syasuko.eckert@amd.com ASSIGN_INT_IF("cache_search_ports", cache_params.cache_search_ports); 51610234Syasuko.eckert@amd.com ASSIGN_INT_IF("miss_buff_rw_ports", cache_params.miss_buff_rw_ports); 51710234Syasuko.eckert@amd.com ASSIGN_INT_IF("miss_buff_rd_ports", cache_params.miss_buff_rd_ports); 51810234Syasuko.eckert@amd.com ASSIGN_INT_IF("miss_buff_wr_ports", cache_params.miss_buff_wr_ports); 51910234Syasuko.eckert@amd.com ASSIGN_INT_IF("miss_buff_se_rd_ports" , 52010234Syasuko.eckert@amd.com cache_params.miss_buff_se_rd_ports); 52110234Syasuko.eckert@amd.com ASSIGN_INT_IF("miss_buff_search_ports", 52210234Syasuko.eckert@amd.com cache_params.miss_buff_search_ports); 52310234Syasuko.eckert@amd.com ASSIGN_INT_IF("fetch_buff_rw_ports", cache_params.fetch_buff_rw_ports); 52410234Syasuko.eckert@amd.com ASSIGN_INT_IF("fetch_buff_rd_ports", cache_params.fetch_buff_rd_ports); 52510234Syasuko.eckert@amd.com ASSIGN_INT_IF("fetch_buff_wr_ports", cache_params.fetch_buff_wr_ports); 52610234Syasuko.eckert@amd.com ASSIGN_INT_IF("fetch_buff_se_rd_ports", 52710234Syasuko.eckert@amd.com cache_params.fetch_buff_se_rd_ports); 52810234Syasuko.eckert@amd.com ASSIGN_INT_IF("fetch_buff_search_ports", 52910234Syasuko.eckert@amd.com cache_params.fetch_buff_search_ports); 53010234Syasuko.eckert@amd.com ASSIGN_INT_IF("pf_buff_rw_ports", cache_params.pf_buff_rw_ports); 53110234Syasuko.eckert@amd.com ASSIGN_INT_IF("pf_buff_rd_ports", cache_params.pf_buff_rd_ports); 53210234Syasuko.eckert@amd.com ASSIGN_INT_IF("pf_buff_wr_ports", cache_params.pf_buff_wr_ports); 53310234Syasuko.eckert@amd.com ASSIGN_INT_IF("pf_buff_se_rd_ports", cache_params.pf_buff_se_rd_ports); 53410234Syasuko.eckert@amd.com ASSIGN_INT_IF("pf_buff_search_ports", 53510234Syasuko.eckert@amd.com cache_params.pf_buff_search_ports); 53610234Syasuko.eckert@amd.com ASSIGN_INT_IF("wb_buff_rw_ports", cache_params.wb_buff_rw_ports); 53710234Syasuko.eckert@amd.com ASSIGN_INT_IF("wb_buff_rd_ports", cache_params.wb_buff_rd_ports); 53810234Syasuko.eckert@amd.com ASSIGN_INT_IF("wb_buff_wr_ports", cache_params.wb_buff_wr_ports); 53910234Syasuko.eckert@amd.com ASSIGN_INT_IF("wb_buff_se_rd_ports", cache_params.wb_buff_se_rd_ports); 54010234Syasuko.eckert@amd.com ASSIGN_INT_IF("wb_buff_search_ports", 54110234Syasuko.eckert@amd.com cache_params.wb_buff_search_ports); 54210234Syasuko.eckert@amd.com ASSIGN_FP_IF("clockrate", cache_params.clockRate); 54310234Syasuko.eckert@amd.com ASSIGN_INT_IF("pure_ram", cache_params.pure_ram); 54410234Syasuko.eckert@amd.com ASSIGN_INT_IF("tech_type", tech_type); 54510234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("Directory_type", cache_params.dir_ty, Dir_type); 54610234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("device_type", cache_params.device_ty, Device_ty); 54710234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("core_type", cache_params.core_ty, Core_type); 54810234Syasuko.eckert@amd.com ASSIGN_INT_IF("num_cores", cache_params.num_cores); 54910234Syasuko.eckert@amd.com ASSIGN_INT_IF("wire_mat_type", mat_type); 55010234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("wire_type", interface_ip.wt, Wire_type); 55110234Syasuko.eckert@amd.com 55210234Syasuko.eckert@amd.com else { 55310234Syasuko.eckert@amd.com warnUnrecognizedParam(node_name); 55410234Syasuko.eckert@amd.com } 55510234Syasuko.eckert@amd.com } 55610234Syasuko.eckert@amd.com 55710234Syasuko.eckert@amd.com // Change from MHz to Hz 55810234Syasuko.eckert@amd.com cache_params.clockRate *= 1e6; 55910234Syasuko.eckert@amd.com if (cache_params.clockRate > 0) { 56010234Syasuko.eckert@amd.com clockRate = cache_params.clockRate; 56110234Syasuko.eckert@amd.com } 56210234Syasuko.eckert@amd.com 56310234Syasuko.eckert@amd.com interface_ip.data_arr_ram_cell_tech_type = tech_type; 56410234Syasuko.eckert@amd.com interface_ip.data_arr_peri_global_tech_type = tech_type; 56510234Syasuko.eckert@amd.com interface_ip.tag_arr_ram_cell_tech_type = tech_type; 56610234Syasuko.eckert@amd.com interface_ip.tag_arr_peri_global_tech_type = tech_type; 56710234Syasuko.eckert@amd.com 56810234Syasuko.eckert@amd.com interface_ip.wire_is_mat_type = mat_type; 56910234Syasuko.eckert@amd.com interface_ip.wire_os_mat_type = mat_type; 57010234Syasuko.eckert@amd.com 57110234Syasuko.eckert@amd.com switch(level) { 57210234Syasuko.eckert@amd.com case 1: 57310234Syasuko.eckert@amd.com cache_params.cache_level = L1; 57410234Syasuko.eckert@amd.com break; 57510234Syasuko.eckert@amd.com case 2: 57610234Syasuko.eckert@amd.com cache_params.cache_level = L2; 57710234Syasuko.eckert@amd.com break; 57810234Syasuko.eckert@amd.com case 3: 57910234Syasuko.eckert@amd.com cache_params.cache_level = L3; 58010234Syasuko.eckert@amd.com break; 58110234Syasuko.eckert@amd.com case 4: 58210234Syasuko.eckert@amd.com cache_params.cache_level = L1Directory; 58310234Syasuko.eckert@amd.com break; 58410234Syasuko.eckert@amd.com case 5: 58510234Syasuko.eckert@amd.com cache_params.cache_level = L2Directory; 58610234Syasuko.eckert@amd.com break; 58710234Syasuko.eckert@amd.com 58810234Syasuko.eckert@amd.com default: 58910234Syasuko.eckert@amd.com fprintf(stderr, "ERROR: Unrecognized cache level in %s: %d\n", 59010234Syasuko.eckert@amd.com name.c_str(), level); 59110234Syasuko.eckert@amd.com exit(1); 59210234Syasuko.eckert@amd.com } 59310234Syasuko.eckert@amd.com 59410234Syasuko.eckert@amd.com cache_stats.use_detailed_stats = false; 59510234Syasuko.eckert@amd.com 59610234Syasuko.eckert@amd.com num_children = xml_data->nChildNode("stat"); 59710234Syasuko.eckert@amd.com for (i = 0; i < num_children; i++) { 59810234Syasuko.eckert@amd.com XMLNode* statNode = xml_data->getChildNodePtr("stat", &i); 59910234Syasuko.eckert@amd.com XMLCSTR node_name = statNode->getAttribute("name"); 60010234Syasuko.eckert@amd.com XMLCSTR value = statNode->getAttribute("value"); 60110234Syasuko.eckert@amd.com 60210234Syasuko.eckert@amd.com if (!node_name) 60310234Syasuko.eckert@amd.com warnMissingStatName(statNode->getAttribute("id")); 60410234Syasuko.eckert@amd.com 60510234Syasuko.eckert@amd.com ASSIGN_FP_IF("num_data_array_reads", cache_stats.num_data_array_reads); 60610234Syasuko.eckert@amd.com ASSIGN_FP_IF("num_data_array_writes", 60710234Syasuko.eckert@amd.com cache_stats.num_data_array_writes); 60810234Syasuko.eckert@amd.com ASSIGN_FP_IF("num_tag_array_reads", cache_stats.num_tag_array_reads); 60910234Syasuko.eckert@amd.com ASSIGN_FP_IF("num_tag_array_writes", cache_stats.num_tag_array_writes); 61010234Syasuko.eckert@amd.com ASSIGN_FP_IF("duty_cycle", cache_stats.duty_cycle); 61110234Syasuko.eckert@amd.com ASSIGN_FP_IF("read_accesses", cache_stats.read_accesses); 61210234Syasuko.eckert@amd.com ASSIGN_FP_IF("write_accesses", cache_stats.write_accesses); 61310234Syasuko.eckert@amd.com ASSIGN_FP_IF("read_misses", cache_stats.read_misses); 61410234Syasuko.eckert@amd.com ASSIGN_FP_IF("write_misses", cache_stats.write_misses); 61510234Syasuko.eckert@amd.com ASSIGN_FP_IF("conflicts", cache_stats.conflicts); 61610234Syasuko.eckert@amd.com ASSIGN_INT_IF("homenode_read_accesses", 61710234Syasuko.eckert@amd.com cache_stats.homenode_read_accesses); 61810234Syasuko.eckert@amd.com ASSIGN_INT_IF("homenode_write_accesses", 61910234Syasuko.eckert@amd.com cache_stats.homenode_write_accesses); 62010234Syasuko.eckert@amd.com ASSIGN_INT_IF("homenode_read_misses", 62110234Syasuko.eckert@amd.com cache_stats.homenode_read_misses); 62210234Syasuko.eckert@amd.com ASSIGN_INT_IF("homenode_write_misses", 62310234Syasuko.eckert@amd.com cache_stats.homenode_write_misses); 62410234Syasuko.eckert@amd.com ASSIGN_FP_IF("homenode_access_scalar", 62510234Syasuko.eckert@amd.com cache_stats.homenode_access_scalar); 62610234Syasuko.eckert@amd.com ASSIGN_FP_IF("tdp_read_access_scalar", 62710234Syasuko.eckert@amd.com cache_stats.tdp_read_access_scalar); 62810234Syasuko.eckert@amd.com ASSIGN_FP_IF("tdp_write_access_scalar", 62910234Syasuko.eckert@amd.com cache_stats.tdp_write_access_scalar); 63010234Syasuko.eckert@amd.com ASSIGN_FP_IF("tdp_sbt_write_access_scalar", 63110234Syasuko.eckert@amd.com cache_stats.tdp_sbt_write_access_scalar); 63210234Syasuko.eckert@amd.com ASSIGN_FP_IF("dir_duty_cycle", 63310234Syasuko.eckert@amd.com cache_stats.dir_duty_cycle); 63410234Syasuko.eckert@amd.com 63510234Syasuko.eckert@amd.com else { 63610234Syasuko.eckert@amd.com warnUnrecognizedStat(node_name); 63710234Syasuko.eckert@amd.com } 63810234Syasuko.eckert@amd.com } 63910234Syasuko.eckert@amd.com 64010234Syasuko.eckert@amd.com if (cache_stats.num_data_array_reads > 0 || 64110234Syasuko.eckert@amd.com cache_stats.num_data_array_writes > 0 || 64210234Syasuko.eckert@amd.com cache_stats.num_tag_array_reads > 0 || 64310234Syasuko.eckert@amd.com cache_stats.num_tag_array_writes > 0) { 64410234Syasuko.eckert@amd.com cache_stats.use_detailed_stats = true; 64510234Syasuko.eckert@amd.com calculate_runtime_data_and_tag = true; 64610234Syasuko.eckert@amd.com } 64710234Syasuko.eckert@amd.com} 648