bus_interconnect.cc revision 10234:5cb711fa6176 
1/*****************************************************************************
2 *                                McPAT
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29 *
30 * Author: Joel Hestness
31 *
32 ***************************************************************************/
33
34#include <algorithm>
35#include <cassert>
36#include <cmath>
37#include <iostream>
38#include <string>
39
40#include "basic_circuit.h"
41#include "bus_interconnect.h"
42#include "common.h"
43#include "const.h"
44#include "io.h"
45#include "parameter.h"
46
47BusInterconnect::BusInterconnect(XMLNode* _xml_data,
48                                 InputParameter* interface_ip_)
49    : McPATComponent(_xml_data), link_bus(NULL), interface_ip(*interface_ip_) {
50    name = "Bus Interconnect";
51    set_param_stats();
52    local_result = init_interface(&interface_ip, name);
53    scktRatio = g_tp.sckt_co_eff;
54
55    interface_ip.throughput = bus_params.link_throughput / bus_params.clockRate;
56    interface_ip.latency = bus_params.link_latency / bus_params.clockRate;
57
58    link_len /= bus_params.total_nodes;
59    if (bus_params.total_nodes > 1) {
60        //All links are shared by neighbors
61        link_len /= 2;
62    }
63
64    link_bus = new Interconnect(xml_data, "Link", Uncore_device,
65                                bus_params.link_base_width,
66                                bus_params.link_base_height,
67                                bus_params.flit_size, link_len, &interface_ip,
68                                bus_params.link_start_wiring_level,
69                                bus_params.clockRate,
70                                bus_params.pipelinable,
71                                bus_params.route_over_perc);
72    children.push_back(link_bus);
73}
74
75void BusInterconnect::computeEnergy() {
76    // Initialize stats for TDP
77    tdp_stats.reset();
78    tdp_stats.readAc.access = bus_stats.duty_cycle;
79    link_bus->int_params.active_ports = bus_params.min_ports - 1;
80    link_bus->int_stats.duty_cycle =
81        bus_params.M_traffic_pattern * bus_stats.duty_cycle;
82
83    // Initialize stats for runtime energy and power
84    rtp_stats.reset();
85    rtp_stats.readAc.access = bus_stats.total_access;
86    link_bus->int_stats.accesses = bus_stats.total_access;
87
88    // Recursively compute energy
89    McPATComponent::computeEnergy();
90}
91
92void BusInterconnect::set_param_stats() {
93    memset(&bus_params, 0, sizeof(BusInterconnectParameters));
94
95    int num_children = xml_data->nChildNode("param");
96    int i;
97    int mat_type;
98    for (i = 0; i < num_children; i++) {
99        XMLNode* paramNode = xml_data->getChildNodePtr("param", &i);
100        XMLCSTR node_name = paramNode->getAttribute("name");
101        XMLCSTR value = paramNode->getAttribute("value");
102
103        if (!node_name)
104            warnMissingParamName(paramNode->getAttribute("id"));
105
106        ASSIGN_FP_IF("clockrate", bus_params.clockRate);
107        ASSIGN_INT_IF("flit_bits", bus_params.flit_size);
108        ASSIGN_FP_IF("link_throughput", bus_params.link_throughput);
109        ASSIGN_FP_IF("link_latency", bus_params.link_latency);
110        ASSIGN_INT_IF("total_nodes", bus_params.total_nodes);
111        ASSIGN_INT_IF("input_ports", bus_params.input_ports);
112        ASSIGN_INT_IF("output_ports", bus_params.output_ports);
113        ASSIGN_INT_IF("global_linked_ports", bus_params.global_linked_ports);
114        ASSIGN_FP_IF("chip_coverage", bus_params.chip_coverage);
115        ASSIGN_INT_IF("pipelinable", bus_params.pipelinable);
116        ASSIGN_FP_IF("link_routing_over_percentage",
117                     bus_params.route_over_perc);
118        ASSIGN_INT_IF("virtual_channel_per_port",
119                      bus_params.virtual_channel_per_port);
120        ASSIGN_FP_IF("M_traffic_pattern", bus_params.M_traffic_pattern);
121        ASSIGN_FP_IF("link_len", link_len);
122        ASSIGN_FP_IF("link_base_width", bus_params.link_base_width);
123        ASSIGN_FP_IF("link_base_height", bus_params.link_base_height);
124        ASSIGN_FP_IF("link_start_wiring_level",
125                     bus_params.link_start_wiring_level);
126        ASSIGN_INT_IF("wire_mat_type", mat_type);
127        ASSIGN_ENUM_IF("wire_type", interface_ip.wt, Wire_type);
128
129        else {
130            warnUnrecognizedParam(node_name);
131        }
132    }
133
134    // Change from MHz to Hz
135    bus_params.clockRate *= 1e6;
136
137    interface_ip.wire_is_mat_type = mat_type;
138    interface_ip.wire_os_mat_type = mat_type;
139
140    num_children = xml_data->nChildNode("stat");
141    for (i = 0; i < num_children; i++) {
142        XMLNode* statNode = xml_data->getChildNodePtr("stat", &i);
143        XMLCSTR node_name = statNode->getAttribute("name");
144        XMLCSTR value = statNode->getAttribute("value");
145
146        if (!node_name)
147            warnMissingStatName(statNode->getAttribute("id"));
148
149        ASSIGN_FP_IF("duty_cycle", bus_stats.duty_cycle);
150        ASSIGN_FP_IF("total_accesses", bus_stats.total_access);
151
152        else {
153            warnUnrecognizedStat(node_name);
154        }
155    }
156
157    clockRate = bus_params.clockRate;
158    bus_params.min_ports =
159        min(bus_params.input_ports, bus_params.output_ports);
160
161    assert(bus_params.chip_coverage <= 1);
162    assert(bus_params.route_over_perc <= 1);
163    assert(link_len > 0);
164}
165
166void
167BusInterconnect::set_duty_cycle(double duty_cycle) {
168    bus_stats.duty_cycle = duty_cycle;
169}
170
171void
172BusInterconnect::set_number_of_accesses(double total_accesses) {
173    bus_stats.total_access = total_accesses;
174}
175
176BusInterconnect::~BusInterconnect() {
177    delete link_bus;
178    link_bus = NULL;
179}
180