arch_const.h revision 10152:52c552138ba1
15625Sgblack@eecs.umich.edu/*****************************************************************************
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305625Sgblack@eecs.umich.edu ***************************************************************************/
315625Sgblack@eecs.umich.edu
325625Sgblack@eecs.umich.edu#ifndef ARCH_CONST_H_
335625Sgblack@eecs.umich.edu#define ARCH_CONST_H_
345625Sgblack@eecs.umich.edu
355625Sgblack@eecs.umich.edutypedef struct{
365625Sgblack@eecs.umich.edu        unsigned int capacity;
375625Sgblack@eecs.umich.edu        unsigned int assoc;//fully
385625Sgblack@eecs.umich.edu        unsigned int blocksize;
395625Sgblack@eecs.umich.edu} array_inputs;
405625Sgblack@eecs.umich.edu
415625Sgblack@eecs.umich.edu//Do Not change, unless you want to bypass the XML interface and do not care about the default values.
425625Sgblack@eecs.umich.edu//Global parameters
435625Sgblack@eecs.umich.educonst int  			number_of_cores =	8;
445625Sgblack@eecs.umich.educonst int  			number_of_L2s 	=	1;
455625Sgblack@eecs.umich.educonst int 			number_of_L3s	=	1;
465625Sgblack@eecs.umich.educonst int 			number_of_NoCs	=	1;
475625Sgblack@eecs.umich.edu
485625Sgblack@eecs.umich.educonst double 		archi_F_sz_nm	=	90.0;
495625Sgblack@eecs.umich.educonst unsigned int 	dev_type		=	0;
505625Sgblack@eecs.umich.educonst double 		CLOCKRATE 		= 	1.2*1e9;
515625Sgblack@eecs.umich.educonst double 		AF 				= 	0.5;
528229Snate@binkert.org//const bool 			inorder			=	true;
535625Sgblack@eecs.umich.educonst bool			embedded		=	false; //NEW
548706Sandreas.hansson@arm.com
555625Sgblack@eecs.umich.educonst bool 			homogeneous_cores	= 	true;
565625Sgblack@eecs.umich.educonst bool 			temperature		=	360;
575625Sgblack@eecs.umich.educonst int			number_cache_levels	=	3;
585625Sgblack@eecs.umich.educonst int			L1_property		=	0; //private 0; coherent 1, shared 2.
595625Sgblack@eecs.umich.educonst int		 	L2_property		=	2;
605625Sgblack@eecs.umich.educonst bool	    	homogeneous_L2s	=	true;
615625Sgblack@eecs.umich.educonst bool		    L3_property		= 	2;
625625Sgblack@eecs.umich.educonst bool 			homogeneous_L3s	=	true;
635625Sgblack@eecs.umich.educonst double 		Max_area_deviation	=	50;
645625Sgblack@eecs.umich.educonst double	    Max_dynamic_deviation	=50; //New
655625Sgblack@eecs.umich.educonst int 			opt_dynamic_power	=	1;
665625Sgblack@eecs.umich.educonst int 			opt_lakage_power	=	0;
675625Sgblack@eecs.umich.educonst int		 	opt_area			=	0;
685625Sgblack@eecs.umich.educonst int			interconnect_projection_type	=	0;
695625Sgblack@eecs.umich.edu
705625Sgblack@eecs.umich.edu//******************************Core Parameters
715625Sgblack@eecs.umich.edu#if (inorder)
725625Sgblack@eecs.umich.educonst int opcode_length			= 	8;//Niagara
735625Sgblack@eecs.umich.educonst int reg_length			=	5;//Niagara
745625Sgblack@eecs.umich.educonst int instruction_length	=	32;//Niagara
755625Sgblack@eecs.umich.educonst int data_width			=	64;
765625Sgblack@eecs.umich.edu#else
775625Sgblack@eecs.umich.educonst int opcode_length			= 	8;//16;//Niagara
785625Sgblack@eecs.umich.educonst int reg_length			=	7;//Niagara
795625Sgblack@eecs.umich.educonst int instruction_length	=	32;//Niagara
805625Sgblack@eecs.umich.educonst int data_width			=	64;
815625Sgblack@eecs.umich.edu#endif
825625Sgblack@eecs.umich.edu
835625Sgblack@eecs.umich.edu
845625Sgblack@eecs.umich.edu//Caches
855625Sgblack@eecs.umich.edu//itlb
865625Sgblack@eecs.umich.educonst int itlbsize=512;
875625Sgblack@eecs.umich.educonst int itlbassoc=0;//fully
885625Sgblack@eecs.umich.educonst int itlbblocksize=8;
895625Sgblack@eecs.umich.edu//icache
905625Sgblack@eecs.umich.educonst int icachesize=32768;
915625Sgblack@eecs.umich.educonst int icacheassoc=4;
925625Sgblack@eecs.umich.educonst int icacheblocksize=32;
935625Sgblack@eecs.umich.edu//dtlb
945625Sgblack@eecs.umich.educonst int dtlbsize=512;
955625Sgblack@eecs.umich.educonst int dtlbassoc=0;//fully
968706Sandreas.hansson@arm.comconst int dtlbblocksize=8;
975625Sgblack@eecs.umich.edu//dcache
985625Sgblack@eecs.umich.educonst int dcachesize=32768;
995625Sgblack@eecs.umich.educonst int dcacheassoc=4;
1005625Sgblack@eecs.umich.educonst int dcacheblocksize=32;
1015625Sgblack@eecs.umich.educonst int dcache_write_buffers=8;
1025625Sgblack@eecs.umich.edu
1035625Sgblack@eecs.umich.edu//cache controllers
1045625Sgblack@eecs.umich.edu//IB,
1055625Sgblack@eecs.umich.educonst int numIBEntries			=	64;
1065625Sgblack@eecs.umich.educonst int IBsize				=	64;//2*4*instruction_length/8*2;
1075625Sgblack@eecs.umich.educonst int IBassoc				=	0;//In Niagara it is still fully associ
1085625Sgblack@eecs.umich.educonst int IBblocksize			=	4;
1095625Sgblack@eecs.umich.edu
1105625Sgblack@eecs.umich.edu//IFB and MIL should have the same parameters CAM
1115625Sgblack@eecs.umich.educonst int IFBsize=128;//
1125625Sgblack@eecs.umich.educonst int IFBassoc=0;//In Niagara it is still fully associ
1135625Sgblack@eecs.umich.educonst int IFBblocksize=4;
1145625Sgblack@eecs.umich.edu
1155625Sgblack@eecs.umich.edu
1165625Sgblack@eecs.umich.edu
1175625Sgblack@eecs.umich.edu
1185625Sgblack@eecs.umich.educonst int icache_write_buffers=8;
1195625Sgblack@eecs.umich.edu
1208706Sandreas.hansson@arm.com//register file RAM
1215625Sgblack@eecs.umich.educonst int regfilesize=5760;
1225625Sgblack@eecs.umich.educonst int regfileassoc=1;
1235625Sgblack@eecs.umich.educonst int regfileblocksize=18;
1245625Sgblack@eecs.umich.edu//regwin  RAM
1255625Sgblack@eecs.umich.educonst int regwinsize=256;
1265625Sgblack@eecs.umich.educonst int regwinassoc=1;
1275625Sgblack@eecs.umich.educonst int regwinblocksize=8;
1285625Sgblack@eecs.umich.edu
1295625Sgblack@eecs.umich.edu
1305625Sgblack@eecs.umich.edu
1315625Sgblack@eecs.umich.edu//store buffer, lsq
1325625Sgblack@eecs.umich.educonst int lsqsize=512;
1335625Sgblack@eecs.umich.educonst int lsqassoc=0;
1345625Sgblack@eecs.umich.educonst int lsqblocksize=8;
1358706Sandreas.hansson@arm.com
1365625Sgblack@eecs.umich.edu//data fill queue RAM
1375625Sgblack@eecs.umich.educonst int dfqsize=1024;
1385625Sgblack@eecs.umich.educonst int dfqassoc=1;
1395625Sgblack@eecs.umich.educonst int dfqblocksize=16;
1405625Sgblack@eecs.umich.edu
1415625Sgblack@eecs.umich.edu//outside the cores
1425625Sgblack@eecs.umich.edu//L2 cache bank
1435625Sgblack@eecs.umich.educonst int l2cachesize=262144;
1445625Sgblack@eecs.umich.educonst int l2cacheassoc=16;
1455625Sgblack@eecs.umich.educonst int l2cacheblocksize=64;
1465625Sgblack@eecs.umich.edu
1475625Sgblack@eecs.umich.edu//L2 directory
1485625Sgblack@eecs.umich.educonst int l2dirsize=1024;
1495625Sgblack@eecs.umich.educonst int l2dirassoc=0;
1505625Sgblack@eecs.umich.educonst int l2dirblocksize=2;
1515625Sgblack@eecs.umich.edu
1525625Sgblack@eecs.umich.edu//crossbar
1535625Sgblack@eecs.umich.edu//PCX
1545625Sgblack@eecs.umich.educonst int PCX_NUMBER_INPUT_PORTS_CROSSBAR = 8;
1555625Sgblack@eecs.umich.educonst int PCX_NUMBER_OUTPUT_PORTS_CROSSBAR = 9;
1565625Sgblack@eecs.umich.educonst int PCX_NUMBER_SIGNALS_PER_PORT_CROSSBAR =144;
1575625Sgblack@eecs.umich.edu//PCX buffer RAM
1588706Sandreas.hansson@arm.comconst int pcx_buffersize=1024;
1595625Sgblack@eecs.umich.educonst int pcx_bufferassoc=1;
1605625Sgblack@eecs.umich.educonst int pcx_bufferblocksize=32;
1615625Sgblack@eecs.umich.educonst int pcx_numbuffer=5;
1625625Sgblack@eecs.umich.edu//pcx arbiter
1635625Sgblack@eecs.umich.educonst int pcx_arbsize=128;
1645625Sgblack@eecs.umich.educonst int pcx_arbassoc=1;
1655625Sgblack@eecs.umich.educonst int pcx_arbblocksize=2;
1665625Sgblack@eecs.umich.educonst int pcx_numarb=5;
1675625Sgblack@eecs.umich.edu
1685625Sgblack@eecs.umich.edu//CPX
1695625Sgblack@eecs.umich.educonst int CPX_NUMBER_INPUT_PORTS_CROSSBAR = 5;
1705625Sgblack@eecs.umich.educonst int CPX_NUMBER_OUTPUT_PORTS_CROSSBAR = 8;
1715625Sgblack@eecs.umich.educonst int CPX_NUMBER_SIGNALS_PER_PORT_CROSSBAR =150;
1725625Sgblack@eecs.umich.edu//CPX buffer RAM
1735625Sgblack@eecs.umich.educonst int cpx_buffersize=1024;
1745625Sgblack@eecs.umich.educonst int cpx_bufferassoc=1;
1758706Sandreas.hansson@arm.comconst int cpx_bufferblocksize=32;
1765625Sgblack@eecs.umich.educonst int cpx_numbuffer=8;
1775625Sgblack@eecs.umich.edu//cpx arbiter
1785625Sgblack@eecs.umich.educonst int cpx_arbsize=128;
1795625Sgblack@eecs.umich.educonst int cpx_arbassoc=1;
1805625Sgblack@eecs.umich.educonst int cpx_arbblocksize=2;
1815625Sgblack@eecs.umich.educonst int cpx_numarb=8;
1825625Sgblack@eecs.umich.edu
1835625Sgblack@eecs.umich.edu
1845625Sgblack@eecs.umich.edu
1855625Sgblack@eecs.umich.edu
1865625Sgblack@eecs.umich.edu
1875625Sgblack@eecs.umich.educonst int numPhysFloatRegs=256;
1885625Sgblack@eecs.umich.educonst int numPhysIntRegs=32;
1898706Sandreas.hansson@arm.comconst int numROBEntries=192;
1905625Sgblack@eecs.umich.educonst int umRobs=1;
1915625Sgblack@eecs.umich.edu
1925625Sgblack@eecs.umich.educonst int BTBEntries=4096;
1935625Sgblack@eecs.umich.educonst int BTBTagSize=16;
1945625Sgblack@eecs.umich.educonst int LFSTSize=1024;
1955625Sgblack@eecs.umich.educonst int LQEntries=32;
1965625Sgblack@eecs.umich.educonst int RASSize=16;
1975625Sgblack@eecs.umich.educonst int SQEntries=32;
1985625Sgblack@eecs.umich.educonst int SSITSize=1024;
1995625Sgblack@eecs.umich.educonst int activity=0;
2005625Sgblack@eecs.umich.educonst int backComSize=5;
2015625Sgblack@eecs.umich.educonst int cachePorts=200;
2025625Sgblack@eecs.umich.educonst int choiceCtrBits=2;
2035625Sgblack@eecs.umich.educonst int choicePredictorSize=8192;
2045625Sgblack@eecs.umich.edu
2058706Sandreas.hansson@arm.com
2065625Sgblack@eecs.umich.educonst int commitWidth=8;
2075625Sgblack@eecs.umich.educonst int decodeWidth=8;
2085625Sgblack@eecs.umich.educonst int dispatchWidth=8;
2095625Sgblack@eecs.umich.educonst int fetchWidth=8;
2105625Sgblack@eecs.umich.educonst int issueWidth=1;
2115625Sgblack@eecs.umich.educonst int renameWidth=8;
2125625Sgblack@eecs.umich.edu//what is this forwardComSize=5??
2135625Sgblack@eecs.umich.edu
2145625Sgblack@eecs.umich.educonst int globalCtrBits=2;
2155625Sgblack@eecs.umich.educonst int globalHistoryBits=13;
2165625Sgblack@eecs.umich.educonst int globalPredictorSize=8192;
2175625Sgblack@eecs.umich.edu
2185625Sgblack@eecs.umich.edu
2195625Sgblack@eecs.umich.edu
2205625Sgblack@eecs.umich.educonst int localCtrBits=2;
2215625Sgblack@eecs.umich.educonst int localHistoryBits=11;
2225625Sgblack@eecs.umich.educonst int localHistoryTableSize=2048;
2235625Sgblack@eecs.umich.educonst int localPredictorSize=2048;
2248706Sandreas.hansson@arm.com
2255625Sgblack@eecs.umich.educonst double Woutdrvnandn	=30 *0.09;//(24.0 * LSCALE)
2265625Sgblack@eecs.umich.educonst double Woutdrvnandp	=12.5 *0.09;//(10.0 * LSCALE)
2275625Sgblack@eecs.umich.educonst double Woutdrvnorn	=7.5*0.09;//(6.0 * LSCALE)
2285625Sgblack@eecs.umich.educonst double Woutdrvnorp  =50 * 0.09;//	(40.0 * LSCALE)
2295625Sgblack@eecs.umich.educonst double Woutdrivern	=60*0.09;//(48.0 * LSCALE)
2305625Sgblack@eecs.umich.educonst double Woutdriverp	=100 * 0.09;//(80.0 * LSCALE)
2315625Sgblack@eecs.umich.edu
2325625Sgblack@eecs.umich.edu/*
2335625Sgblack@eecs.umich.edusmtCommitPolicy=RoundRobin
2345625Sgblack@eecs.umich.edusmtFetchPolicy=SingleThread
2355625Sgblack@eecs.umich.edusmtIQPolicy=Partitioned
2365625Sgblack@eecs.umich.edusmtIQThreshold=100
2375625Sgblack@eecs.umich.edusmtLSQPolicy=Partitioned
2385625Sgblack@eecs.umich.edusmtLSQThreshold=100
2395625Sgblack@eecs.umich.edusmtNumFetchingThreads=1
2405625Sgblack@eecs.umich.edusmtROBPolicy=Partitioned
2415625Sgblack@eecs.umich.edusmtROBThreshold=100
2425625Sgblack@eecs.umich.edusquashWidth=8
2435625Sgblack@eecs.umich.edu*/
2445625Sgblack@eecs.umich.edu
2455625Sgblack@eecs.umich.edu/*
2465625Sgblack@eecs.umich.eduprefetch_access=false
2475625Sgblack@eecs.umich.eduprefetch_cache_check_push=true
2485625Sgblack@eecs.umich.eduprefetch_data_accesses_only=false
2495625Sgblack@eecs.umich.eduprefetch_degree=1
2505625Sgblack@eecs.umich.eduprefetch_latency=10000
2515625Sgblack@eecs.umich.eduprefetch_miss=false
2525625Sgblack@eecs.umich.eduprefetch_past_page=false
2535625Sgblack@eecs.umich.eduprefetch_policy=none
2545625Sgblack@eecs.umich.eduprefetch_serial_squash=false
2555625Sgblack@eecs.umich.eduprefetch_use_cpu_id=true
2565625Sgblack@eecs.umich.eduprefetcher_size=100
2575625Sgblack@eecs.umich.eduprioritizeRequests=false
2585625Sgblack@eecs.umich.edurepl=Null
2595625Sgblack@eecs.umich.edu
2605625Sgblack@eecs.umich.edu
2615625Sgblack@eecs.umich.edusplit=false
2625625Sgblack@eecs.umich.edusplit_size=0
2635625Sgblack@eecs.umich.edusubblock_size=0
2645625Sgblack@eecs.umich.edutgts_per_mshr=20
2655625Sgblack@eecs.umich.edutrace_addr=0
2665625Sgblack@eecs.umich.edutwo_queue=false
2675625Sgblack@eecs.umich.edu
2685625Sgblack@eecs.umich.educpu_side=system.cpu0.dcache_port
2695625Sgblack@eecs.umich.edumem_side=system.tol2bus.port[2]
2705625Sgblack@eecs.umich.edu*/
2715625Sgblack@eecs.umich.edu
2728706Sandreas.hansson@arm.com//[system.cpu0.dtb]
2735625Sgblack@eecs.umich.edu//type=AlphaDT
2745625Sgblack@eecs.umich.edu
2755625Sgblack@eecs.umich.edu
2765625Sgblack@eecs.umich.edu#endif /* ARCH_CONST_H_ */
2775625Sgblack@eecs.umich.edu