110152Satgutier@umich.edu<?xml version="1.0" ?> 210152Satgutier@umich.edu<component id="root" name="root"> 310152Satgutier@umich.edu <component id="system" name="system"> 410152Satgutier@umich.edu <!--McPAT will skip the components if number is set to 0 --> 510152Satgutier@umich.edu <param name="number_of_cores" value="8"/> 610152Satgutier@umich.edu <param name="number_of_L1Directories" value="8"/> 710152Satgutier@umich.edu <param name="number_of_L2Directories" value="0"/> 810152Satgutier@umich.edu <param name="number_of_L2s" value="8"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports --> 910152Satgutier@umich.edu <param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters --> 1010152Satgutier@umich.edu <param name="number_of_NoCs" value="1"/> 1110152Satgutier@umich.edu <param name="homogeneous_cores" value="1"/><!--1 means homo --> 1210152Satgutier@umich.edu <param name="homogeneous_L2s" value="1"/> 1310152Satgutier@umich.edu <param name="homogeneous_L1Directorys" value="1"/> 1410152Satgutier@umich.edu <param name="homogeneous_L2Directorys" value="1"/> 1510152Satgutier@umich.edu <param name="homogeneous_L3s" value="1"/> 1610152Satgutier@umich.edu <param name="homogeneous_ccs" value="1"/><!--cache coherece hardware --> 1710152Satgutier@umich.edu <param name="homogeneous_NoCs" value="1"/> 1810152Satgutier@umich.edu <param name="core_tech_node" value="65"/><!-- nm --> 1910152Satgutier@umich.edu <param name="target_core_clockrate" value="1400"/><!--MHz --> 2010152Satgutier@umich.edu <param name="temperature" value="380"/> <!-- Kelvin --> 2110152Satgutier@umich.edu <param name="number_cache_levels" value="2"/> 2210152Satgutier@umich.edu <param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology --> 2310152Satgutier@umich.edu <param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power) --> 2410152Satgutier@umich.edu <param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible --> 2510152Satgutier@umich.edu <param name="machine_bits" value="64"/> 2610152Satgutier@umich.edu <param name="virtual_address_width" value="64"/> 2710152Satgutier@umich.edu <param name="physical_address_width" value="52"/> 2810152Satgutier@umich.edu <param name="virtual_memory_page_size" value="4096"/> 2910152Satgutier@umich.edu <stat name="total_cycles" value="100000"/> 3010152Satgutier@umich.edu <stat name="idle_cycles" value="0"/> 3110152Satgutier@umich.edu <stat name="busy_cycles" value="100000"/> 3210152Satgutier@umich.edu <!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of 3310152Satgutier@umich.edu virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank --> 3410152Satgutier@umich.edu <!-- *********************** cores ******************* --> 3510152Satgutier@umich.edu <component id="system.core0" name="core0"> 3610152Satgutier@umich.edu <!-- Core property --> 3710152Satgutier@umich.edu <param name="clock_rate" value="1400"/> 3810152Satgutier@umich.edu <param name="instruction_length" value="32"/> 3910152Satgutier@umich.edu <param name="opcode_width" value="9"/> 4010152Satgutier@umich.edu <!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller 4110152Satgutier@umich.edu default value is machine_bits, if not set --> 4210152Satgutier@umich.edu <param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO--> 4310152Satgutier@umich.edu <!-- inorder/OoO --> 4410152Satgutier@umich.edu <param name="number_hardware_threads" value="4"/> 4510152Satgutier@umich.edu <!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor, 4610152Satgutier@umich.edu it only may be more than one in SMT processors. BTB ports always equals to fetch ports since 4710152Satgutier@umich.edu branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> 4810152Satgutier@umich.edu <param name="fetch_width" value="1"/> 4910152Satgutier@umich.edu <!-- fetch_width determins the size of cachelines of L1 cache block --> 5010152Satgutier@umich.edu <param name="number_instruction_fetch_ports" value="1"/> 5110152Satgutier@umich.edu <param name="decode_width" value="1"/> 5210152Satgutier@umich.edu <!-- decode_width determins the number of ports of the 5310152Satgutier@umich.edu renaming table (both RAM and CAM) scheme --> 5410152Satgutier@umich.edu <param name="issue_width" value="1"/> 5510152Satgutier@umich.edu <!-- issue_width determins the number of ports of Issue window and other logic 5610152Satgutier@umich.edu as in the complexity effective proccessors paper; issue_width==dispatch_width --> 5710152Satgutier@umich.edu <param name="commit_width" value="1"/> 5810152Satgutier@umich.edu <!-- commit_width determins the number of ports of register files --> 5910152Satgutier@umich.edu <param name="fp_issue_width" value="1"/> 6010152Satgutier@umich.edu <param name="prediction_width" value="0"/> 6110152Satgutier@umich.edu <!-- number of branch instructions can be predicted simultannouesl--> 6210152Satgutier@umich.edu <!-- Current version of McPAT does not distinguish int and floating point pipelines 6310152Satgutier@umich.edu Theses parameters are reserved for future use.--> 6410152Satgutier@umich.edu <param name="pipelines_per_core" value="2,1"/> 6510152Satgutier@umich.edu <!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared--> 6610152Satgutier@umich.edu <param name="pipeline_depth" value="8,8"/> 6710152Satgutier@umich.edu <!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops --> 6810152Satgutier@umich.edu <!-- issue and exe unit--> 6910152Satgutier@umich.edu <param name="ALU_per_core" value="2"/> 7010152Satgutier@umich.edu <!-- contains an adder, a shifter, and a logical unit --> 7110152Satgutier@umich.edu <param name="MUL_per_core" value="0"/> 7210152Satgutier@umich.edu <!-- For MUL and Div --> 7310152Satgutier@umich.edu <param name="FPU_per_core" value="1"/> 7410152Satgutier@umich.edu <!-- buffer between IF and ID stage --> 7510152Satgutier@umich.edu <param name="instruction_buffer_size" value="32"/> 7610152Satgutier@umich.edu <!-- buffer between ID and sche/exe stage --> 7710152Satgutier@umich.edu <param name="decoded_stream_buffer_size" value="16"/> 7810152Satgutier@umich.edu <param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED--> 7910152Satgutier@umich.edu <!-- McPAT support 2 types of OoO cores, RS based and physical reg based--> 8010152Satgutier@umich.edu <param name="instruction_window_size" value="16"/> 8110152Satgutier@umich.edu <param name="fp_instruction_window_size" value="16"/> 8210152Satgutier@umich.edu <!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 --> 8310152Satgutier@umich.edu <param name="ROB_size" value="80"/> 8410152Satgutier@umich.edu <!-- each in-flight instruction has an entry in ROB --> 8510152Satgutier@umich.edu <!-- registers --> 8610152Satgutier@umich.edu <param name="archi_Regs_IRF_size" value="32"/> 8710152Satgutier@umich.edu <param name="archi_Regs_FRF_size" value="32"/> 8810152Satgutier@umich.edu <!-- if OoO processor, phy_reg number is needed for renaming logic, 8910152Satgutier@umich.edu renaming logic is for both integer and floating point insts. --> 9010152Satgutier@umich.edu <param name="phy_Regs_IRF_size" value="80"/> 9110152Satgutier@umich.edu <param name="phy_Regs_FRF_size" value="80"/> 9210152Satgutier@umich.edu <!-- rename logic --> 9310152Satgutier@umich.edu <param name="rename_scheme" value="0"/> 9410152Satgutier@umich.edu <!-- can be RAM based(0) or CAM based(1) rename scheme 9510152Satgutier@umich.edu RAM-based scheme will have free list, status table; 9610152Satgutier@umich.edu CAM-based scheme have the valid bit in the data field of the CAM 9710152Satgutier@umich.edu both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions; 9810152Satgutier@umich.edu Detailed RAT Implementation see TR --> 9910152Satgutier@umich.edu <param name="register_windows_size" value="8"/> 10010152Satgutier@umich.edu <!-- how many windows in the windowed register file, sun processors; 10110152Satgutier@umich.edu no register windowing is used when this number is 0 --> 10210152Satgutier@umich.edu <!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha), 10310152Satgutier@umich.edu They will always try to exeute out-of-order though. --> 10410152Satgutier@umich.edu <param name="LSU_order" value="inorder"/> 10510152Satgutier@umich.edu <param name="store_buffer_size" value="64"/> 10610152Satgutier@umich.edu <!-- By default, in-order cores do not have load buffers --> 10710152Satgutier@umich.edu <param name="load_buffer_size" value="64"/> 10810152Satgutier@umich.edu <!-- number of ports refer to sustainable concurrent memory accesses --> 10910152Satgutier@umich.edu <param name="memory_ports" value="1"/> 11010152Satgutier@umich.edu <!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer 11110152Satgutier@umich.edu as well as the ports of Dcache which is connected to LSU --> 11210152Satgutier@umich.edu <!-- dual-pumped Dcache can be used to save the extra read/write ports --> 11310152Satgutier@umich.edu <param name="RAS_size" value="32"/> 11410152Satgutier@umich.edu <!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check --> 11510152Satgutier@umich.edu <!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops --> 11610152Satgutier@umich.edu <stat name="total_instructions" value="1600000"/> 11710152Satgutier@umich.edu <stat name="int_instructions" value="1200000"/> 11810152Satgutier@umich.edu <stat name="fp_instructions" value="40000"/> 11910152Satgutier@umich.edu <stat name="branch_instructions" value="0"/> 12010152Satgutier@umich.edu <stat name="branch_mispredictions" value="0"/> 12110152Satgutier@umich.edu <stat name="load_instructions" value="200000"/> 12210152Satgutier@umich.edu <stat name="store_instructions" value="200000"/> 12310152Satgutier@umich.edu <stat name="committed_instructions" value="1600000"/> 12410152Satgutier@umich.edu <stat name="committed_int_instructions" value="1200000"/> 12510152Satgutier@umich.edu <stat name="committed_fp_instructions" value="40000"/> 12610152Satgutier@umich.edu <stat name="pipeline_duty_cycle" value="0.5"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous --> 12710152Satgutier@umich.edu <!-- the following cycle stats are used for heterogeneouse cores only, 12810152Satgutier@umich.edu please ignore them if homogeneouse cores --> 12910152Satgutier@umich.edu <stat name="total_cycles" value="100000"/> 13010152Satgutier@umich.edu <stat name="idle_cycles" value="0"/> 13110152Satgutier@umich.edu <stat name="busy_cycles" value="100000"/> 13210152Satgutier@umich.edu <!-- instruction buffer stats --> 13310152Satgutier@umich.edu <!-- ROB stats, both RS and Phy based OoOs have ROB 13410152Satgutier@umich.edu performance simulator should capture the difference on accesses, 13510152Satgutier@umich.edu otherwise, McPAT has to guess based on number of commited instructions. --> 13610152Satgutier@umich.edu <stat name="ROB_reads" value="263886"/> 13710152Satgutier@umich.edu <stat name="ROB_writes" value="263886"/> 13810152Satgutier@umich.edu <!-- RAT accesses --> 13910152Satgutier@umich.edu <stat name="rename_accesses" value="263886"/> 14010152Satgutier@umich.edu <stat name="fp_rename_accesses" value="263886"/> 14110152Satgutier@umich.edu <!-- decode and rename stage use this, should be total ic - nop --> 14210152Satgutier@umich.edu <!-- Inst window stats --> 14310152Satgutier@umich.edu <stat name="inst_window_reads" value="263886"/> 14410152Satgutier@umich.edu <stat name="inst_window_writes" value="263886"/> 14510152Satgutier@umich.edu <stat name="inst_window_wakeup_accesses" value="263886"/> 14610152Satgutier@umich.edu <stat name="fp_inst_window_reads" value="263886"/> 14710152Satgutier@umich.edu <stat name="fp_inst_window_writes" value="263886"/> 14810152Satgutier@umich.edu <stat name="fp_inst_window_wakeup_accesses" value="263886"/> 14910152Satgutier@umich.edu <!-- RF accesses --> 15010152Satgutier@umich.edu <stat name="int_regfile_reads" value="3200000"/> 15110152Satgutier@umich.edu <stat name="float_regfile_reads" value="80000"/> 15210152Satgutier@umich.edu <stat name="int_regfile_writes" value="1600000"/> 15310152Satgutier@umich.edu <stat name="float_regfile_writes" value="40000"/> 15410152Satgutier@umich.edu <!-- accesses to the working reg --> 15510152Satgutier@umich.edu <stat name="function_calls" value="5"/> 15610152Satgutier@umich.edu <stat name="context_switches" value="260343"/> 15710152Satgutier@umich.edu <!-- Number of Windowes switches (number of function calls and returns)--> 15810152Satgutier@umich.edu <!-- Alu stats by default, the processor has one FPU that includes the divider and 15910152Satgutier@umich.edu multiplier. The fpu accesses should include accesses to multiplier and divider --> 16010152Satgutier@umich.edu <stat name="ialu_accesses" value="1600000"/> 16110152Satgutier@umich.edu <stat name="fpu_accesses" value="10000"/> 16210152Satgutier@umich.edu <stat name="mul_accesses" value="100000"/> 16310152Satgutier@umich.edu <stat name="cdb_alu_accesses" value="1200000"/> 16410152Satgutier@umich.edu <stat name="cdb_mul_accesses" value="0"/> 16510152Satgutier@umich.edu <stat name="cdb_fpu_accesses" value="0"/> 16610152Satgutier@umich.edu <!-- multiple cycle accesses should be counted multiple times, 16710152Satgutier@umich.edu otherwise, McPAT can use internal counter for different floating point instructions 16810152Satgutier@umich.edu to get final accesses. But that needs detailed info for floating point inst mix --> 16910152Satgutier@umich.edu <!-- currently the performance simulator should 17010152Satgutier@umich.edu make sure all the numbers are final numbers, 17110152Satgutier@umich.edu including the explicit read/write accesses, 17210152Satgutier@umich.edu and the implicite accesses such as replacements and etc. 17310152Satgutier@umich.edu Future versions of McPAT may be able to reason the implicite access 17410152Satgutier@umich.edu based on param and stats of last level cache 17510152Satgutier@umich.edu The same rule applies to all cache access stats too! --> 17610152Satgutier@umich.edu <!-- following is AF for max power computation. 17710152Satgutier@umich.edu Do not change them, unless you understand them--> 17810152Satgutier@umich.edu <stat name="IFU_duty_cycle" value="0.5"/> 17910152Satgutier@umich.edu <stat name="LSU_duty_cycle" value="0.25"/> 18010152Satgutier@umich.edu <stat name="MemManU_I_duty_cycle" value="0.5"/> 18110152Satgutier@umich.edu <stat name="MemManU_D_duty_cycle" value="0.25"/> 18210152Satgutier@umich.edu <stat name="ALU_duty_cycle" value="0.9"/> 18310152Satgutier@umich.edu <stat name="MUL_duty_cycle" value="0"/> 18410152Satgutier@umich.edu <stat name="FPU_duty_cycle" value="0.6"/> 18510152Satgutier@umich.edu <!--FPU also handles Mul/div --> 18610152Satgutier@umich.edu <stat name="ALU_cdb_duty_cycle" value="0.9"/> 18710152Satgutier@umich.edu <stat name="MUL_cdb_duty_cycle" value="0"/> 18810152Satgutier@umich.edu <stat name="FPU_cdb_duty_cycle" value="0.6"/> 18910152Satgutier@umich.edu <component id="system.core0.predictor" name="PBT"> 19010152Satgutier@umich.edu <!-- branch predictor; tournament predictor see Alpha implementation --> 19110152Satgutier@umich.edu <param name="local_predictor_size" value="10,3"/> 19210152Satgutier@umich.edu <param name="local_predictor_entries" value="1024"/> 19310152Satgutier@umich.edu <param name="global_predictor_entries" value="4096"/> 19410152Satgutier@umich.edu <param name="global_predictor_bits" value="2"/> 19510152Satgutier@umich.edu <param name="chooser_predictor_entries" value="4096"/> 19610152Satgutier@umich.edu <param name="chooser_predictor_bits" value="2"/> 19710152Satgutier@umich.edu <!-- These parameters can be combined like below in next version 19810152Satgutier@umich.edu <param name="load_predictor" value="10,3,1024"/> 19910152Satgutier@umich.edu <param name="global_predictor" value="4096,2"/> 20010152Satgutier@umich.edu <param name="predictor_chooser" value="4096,2"/> 20110152Satgutier@umich.edu --> 20210152Satgutier@umich.edu </component> 20310152Satgutier@umich.edu <component id="system.core0.itlb" name="itlb"> 20410152Satgutier@umich.edu <param name="number_entries" value="64"/> 20510152Satgutier@umich.edu <stat name="total_accesses" value="800000"/> 20610152Satgutier@umich.edu <stat name="total_misses" value="4"/> 20710152Satgutier@umich.edu <stat name="conflicts" value="0"/> 20810152Satgutier@umich.edu <!-- there is no write requests to itlb although writes happen to itlb after miss, 20910152Satgutier@umich.edu which is actually a replacement --> 21010152Satgutier@umich.edu </component> 21110152Satgutier@umich.edu <component id="system.core0.icache" name="icache"> 21210152Satgutier@umich.edu <!-- there is no write requests to itlb although writes happen to it after miss, 21310152Satgutier@umich.edu which is actually a replacement --> 21410152Satgutier@umich.edu <param name="icache_config" value="16384,32,8,1,1,7,8,0"/> 21510152Satgutier@umich.edu <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> 21610152Satgutier@umich.edu <!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate --> 21710152Satgutier@umich.edu <param name="buffer_sizes" value="16, 16, 16,0"/> 21810152Satgutier@umich.edu <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 21910152Satgutier@umich.edu <stat name="read_accesses" value="200000"/> 22010152Satgutier@umich.edu <stat name="read_misses" value="0"/> 22110152Satgutier@umich.edu <stat name="conflicts" value="0"/> 22210152Satgutier@umich.edu </component> 22310152Satgutier@umich.edu <component id="system.core0.dtlb" name="dtlb"> 22410152Satgutier@umich.edu <param name="number_entries" value="128"/> 22510152Satgutier@umich.edu <stat name="total_accesses" value="200000"/> 22610152Satgutier@umich.edu <stat name="total_misses" value="4"/> 22710152Satgutier@umich.edu <stat name="conflicts" value="0"/> 22810152Satgutier@umich.edu </component> 22910152Satgutier@umich.edu <component id="system.core0.dcache" name="dcache"> 23010152Satgutier@umich.edu <!-- all the buffer related are optional --> 23110152Satgutier@umich.edu <param name="dcache_config" value="8192,16,4,1, 1,3, 16,0"/> 23210152Satgutier@umich.edu <param name="buffer_sizes" value="16, 16, 16, 16"/> 23310152Satgutier@umich.edu <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 23410152Satgutier@umich.edu <stat name="read_accesses" value="200000"/> 23510152Satgutier@umich.edu <stat name="write_accesses" value="27276"/> 23610152Satgutier@umich.edu <stat name="read_misses" value="1632"/> 23710152Satgutier@umich.edu <stat name="write_misses" value="183"/> 23810152Satgutier@umich.edu <stat name="conflicts" value="0"/> 23910152Satgutier@umich.edu </component> 24010152Satgutier@umich.edu <component id="system.core0.BTB" name="BTB"> 24110152Satgutier@umich.edu <!-- all the buffer related are optional --> 24210152Satgutier@umich.edu <param name="BTB_config" value="8192,4,2,1, 1,3"/> 24310152Satgutier@umich.edu <!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> 24410152Satgutier@umich.edu </component> 24510152Satgutier@umich.edu </component> 24610152Satgutier@umich.edu <component id="system.L1Directory0" name="L1Directory0"> 24710152Satgutier@umich.edu <param name="Directory_type" value="0"/> 24810152Satgutier@umich.edu <!--0 cam based shadowed tag. 1 directory cache --> 24910152Satgutier@umich.edu <param name="Dir_config" value="1024,2,0,1,1,1, 8"/> 25010152Satgutier@umich.edu <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> 25110152Satgutier@umich.edu <param name="buffer_sizes" value="8, 8, 8, 8"/> 25210152Satgutier@umich.edu <!-- all the buffer related are optional --> 25310152Satgutier@umich.edu <param name="clockrate" value="1400"/> 25410152Satgutier@umich.edu <param name="ports" value="1,1,1"/> 25510152Satgutier@umich.edu <!-- number of r, w, and rw search ports --> 25610152Satgutier@umich.edu <param name="device_type" value="0"/> 25710152Satgutier@umich.edu <!-- altough there are multiple access types, 25810152Satgutier@umich.edu Performance simulator needs to cast them into reads or writes 25910152Satgutier@umich.edu e.g. the invalidates can be considered as writes --> 26010152Satgutier@umich.edu <stat name="read_accesses" value="800000"/> 26110152Satgutier@umich.edu <stat name="write_accesses" value="27276"/> 26210152Satgutier@umich.edu <stat name="read_misses" value="1632"/> 26310152Satgutier@umich.edu <stat name="write_misses" value="183"/> 26410152Satgutier@umich.edu <stat name="conflicts" value="20"/> 26510152Satgutier@umich.edu </component> 26610152Satgutier@umich.edu <component id="system.L2Directory0" name="L2Directory0"> 26710152Satgutier@umich.edu <param name="Directory_type" value="1"/> 26810152Satgutier@umich.edu <!--0 cam based shadowed tag. 1 directory cache --> 26910152Satgutier@umich.edu <param name="Dir_config" value="1048576,16,16,1,2, 100"/> 27010152Satgutier@umich.edu <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> 27110152Satgutier@umich.edu <param name="buffer_sizes" value="8, 8, 8, 8"/> 27210152Satgutier@umich.edu <!-- all the buffer related are optional --> 27310152Satgutier@umich.edu <param name="clockrate" value="1400"/> 27410152Satgutier@umich.edu <param name="ports" value="1,1,1"/> 27510152Satgutier@umich.edu <!-- number of r, w, and rw search ports --> 27610152Satgutier@umich.edu <param name="device_type" value="0"/> 27710152Satgutier@umich.edu <!-- altough there are multiple access types, 27810152Satgutier@umich.edu Performance simulator needs to cast them into reads or writes 27910152Satgutier@umich.edu e.g. the invalidates can be considered as writes --> 28010152Satgutier@umich.edu <stat name="read_accesses" value="58824"/> 28110152Satgutier@umich.edu <stat name="write_accesses" value="27276"/> 28210152Satgutier@umich.edu <stat name="read_misses" value="1632"/> 28310152Satgutier@umich.edu <stat name="write_misses" value="183"/> 28410152Satgutier@umich.edu <stat name="conflicts" value="100"/> 28510152Satgutier@umich.edu </component> 28610152Satgutier@umich.edu <component id="system.L20" name="L20"> 28710152Satgutier@umich.edu <!-- all the buffer related are optional --> 28810152Satgutier@umich.edu <param name="L2_config" value="524228,64,16,1, 8,23, 64,1"/> 28910152Satgutier@umich.edu <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> 29010152Satgutier@umich.edu <param name="buffer_sizes" value="16, 16, 16, 16"/> 29110152Satgutier@umich.edu <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 29210152Satgutier@umich.edu <param name="clockrate" value="1400"/> 29310152Satgutier@umich.edu <param name="ports" value="1,1,1"/> 29410152Satgutier@umich.edu <!-- number of r, w, and rw ports --> 29510152Satgutier@umich.edu <param name="device_type" value="0"/> 29610152Satgutier@umich.edu <stat name="read_accesses" value="400000"/> 29710152Satgutier@umich.edu <stat name="write_accesses" value="0"/> 29810152Satgutier@umich.edu <stat name="read_misses" value="0"/> 29910152Satgutier@umich.edu <stat name="write_misses" value="0"/> 30010152Satgutier@umich.edu <stat name="conflicts" value="0"/> 30110152Satgutier@umich.edu <stat name="duty_cycle" value="1"/> 30210152Satgutier@umich.edu </component> 30310152Satgutier@umich.edu 30410152Satgutier@umich.edu<!--**********************************************************************--> 30510152Satgutier@umich.edu<component id="system.L30" name="L30"> 30610152Satgutier@umich.edu <param name="L3_config" value="1048576,64,16,1, 2,100, 64, 1"/> 30710152Satgutier@umich.edu <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> 30810152Satgutier@umich.edu <param name="clockrate" value="3500"/> 30910152Satgutier@umich.edu <param name="ports" value="1,1,1"/> 31010152Satgutier@umich.edu <!-- number of r, w, and rw ports --> 31110152Satgutier@umich.edu <param name="device_type" value="0"/> 31210152Satgutier@umich.edu <param name="buffer_sizes" value="16, 16, 16, 16"/> 31310152Satgutier@umich.edu <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> 31410152Satgutier@umich.edu <stat name="read_accesses" value="58824"/> 31510152Satgutier@umich.edu <stat name="write_accesses" value="27276"/> 31610152Satgutier@umich.edu <stat name="read_misses" value="1632"/> 31710152Satgutier@umich.edu <stat name="write_misses" value="183"/> 31810152Satgutier@umich.edu <stat name="conflicts" value="0"/> 31910152Satgutier@umich.edu <stat name="duty_cycle" value="0.35"/> 32010152Satgutier@umich.edu </component> 32110152Satgutier@umich.edu<!--**********************************************************************--> 32210152Satgutier@umich.edu <component id="system.NoC0" name="noc0"> 32310152Satgutier@umich.edu <param name="clockrate" value="1400"/> 32410152Satgutier@umich.edu <param name="horizontal_nodes" value="2"/> 32510152Satgutier@umich.edu <param name="vertical_nodes" value="1"/> 32610152Satgutier@umich.edu <param name="has_global_link" value="0"/> 32710152Satgutier@umich.edu <!-- 1 has global link, 0 does not have global link --> 32810152Satgutier@umich.edu <param name="link_throughput" value="1"/><!--w.r.t clock --> 32910152Satgutier@umich.edu <param name="link_latency" value="1"/><!--w.r.t clock --> 33010152Satgutier@umich.edu <!-- througput >= latency --> 33110152Satgutier@umich.edu <!-- Router architecture --> 33210152Satgutier@umich.edu <param name="input_ports" value="9"/> 33310152Satgutier@umich.edu <param name="output_ports" value="8"/> 33410152Satgutier@umich.edu <param name="virtual_channel_per_port" value="1"/> 33510152Satgutier@umich.edu <!-- input buffer; in classic routers only input ports need buffers --> 33610152Satgutier@umich.edu <param name="flit_bits" value="136"/> 33710152Satgutier@umich.edu <param name="input_buffer_entries_per_vc" value="16"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs--> 33810152Satgutier@umich.edu <param name="chip_coverage" value="1"/> 33910152Satgutier@umich.edu <!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 --> 34010152Satgutier@umich.edu <stat name="total_accesses" value="160000"/> 34110152Satgutier@umich.edu <!-- This is the number of total accesses within the whole network not for each router --> 34210152Satgutier@umich.edu <stat name="duty_cycle" value="0.1"/> 34310152Satgutier@umich.edu </component> 34410152Satgutier@umich.edu 34510152Satgutier@umich.edu<!--**********************************************************************--> 34610152Satgutier@umich.edu <component id="system.mem" name="mem"> 34710152Satgutier@umich.edu <!-- Main memory property --> 34810152Satgutier@umich.edu <param name="mem_tech_node" value="32"/> 34910152Satgutier@umich.edu <param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB --> 35010152Satgutier@umich.edu <param name="peak_transfer_rate" value="6400"/><!--MB/S--> 35110152Satgutier@umich.edu <param name="internal_prefetch_of_DRAM_chip" value="4"/> 35210152Satgutier@umich.edu <!-- 2 for DDR, 4 for DDR2, 8 for DDR3...--> 35310152Satgutier@umich.edu <!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property --> 35410152Satgutier@umich.edu <!-- above numbers can be easily found from Wikipedia --> 35510152Satgutier@umich.edu <param name="capacity_per_channel" value="4096"/> <!-- MB --> 35610152Satgutier@umich.edu <!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank 35710152Satgutier@umich.edu Current McPAT assumes single DIMMs are used.--> 35810152Satgutier@umich.edu <param name="number_ranks" value="2"/> 35910152Satgutier@umich.edu <param name="num_banks_of_DRAM_chip" value="8"/> 36010152Satgutier@umich.edu <param name="Block_width_of_DRAM_chip" value="64"/> <!-- B --> 36110152Satgutier@umich.edu <param name="output_width_of_DRAM_chip" value="8"/> 36210152Satgutier@umich.edu <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> 36310152Satgutier@umich.edu <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> 36410152Satgutier@umich.edu <param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 --> 36510152Satgutier@umich.edu <param name="burstlength_of_DRAM_chip" value="8"/> 36610152Satgutier@umich.edu <stat name="memory_accesses" value="1052"/> 36710152Satgutier@umich.edu <stat name="memory_reads" value="1052"/> 36810152Satgutier@umich.edu <stat name="memory_writes" value="1052"/> 36910152Satgutier@umich.edu </component> 37010152Satgutier@umich.edu <component id="system.mc" name="mc"> 37110152Satgutier@umich.edu <!-- Memeory controllers are for DDR(2,3...) DIMMs --> 37210152Satgutier@umich.edu <!-- current version of McPAT uses published values for base parameters of memory controller 37310152Satgutier@umich.edu improvments on MC will be added in later versions. --> 37410152Satgutier@umich.edu <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> 37510152Satgutier@umich.edu <param name="mc_clock" value="400"/><!--MHz--> 37610152Satgutier@umich.edu <param name="peak_transfer_rate" value="6400"/><!--MB/S--> 37710152Satgutier@umich.edu <param name="block_size" value="64"/><!--(B) the block size of last level cache, which is the unit for one memory burst transfer --> 37810152Satgutier@umich.edu <param name="number_mcs" value="4"/> 37910152Satgutier@umich.edu <!-- current McPAT only supports homogeneous memory controllers --> 38010152Satgutier@umich.edu <param name="memory_channels_per_mc" value="1"/> 38110152Satgutier@umich.edu <param name="number_ranks" value="2"/> 38210152Satgutier@umich.edu <param name="withPHY" value="0"/> 38310152Satgutier@umich.edu <!-- # of ranks of each channel--> 38410152Satgutier@umich.edu <param name="req_window_size_per_channel" value="32"/> 38510152Satgutier@umich.edu <param name="IO_buffer_size_per_channel" value="32"/> 38610152Satgutier@umich.edu <param name="databus_width" value="128"/> 38710152Satgutier@umich.edu <param name="addressbus_width" value="51"/> 38810152Satgutier@umich.edu <!-- McPAT will add the control bus width to the addressbus width automatically --> 38910152Satgutier@umich.edu <stat name="memory_accesses" value="66666"/> 39010152Satgutier@umich.edu <stat name="memory_reads" value="33333"/> 39110152Satgutier@umich.edu <stat name="memory_writes" value="33333"/> 39210152Satgutier@umich.edu <!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate 39310152Satgutier@umich.edu the average power per MC or per channel. This is sufficent for most application. 39410152Satgutier@umich.edu Further trackdown can be easily added in later versions. --> 39510152Satgutier@umich.edu </component> 39610152Satgutier@umich.edu<!--**********************************************************************--> 39710152Satgutier@umich.edu <component id="system.niu" name="niu"> 39810152Satgutier@umich.edu <!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller --> 39910152Satgutier@umich.edu <!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. 40010152Satgutier@umich.edu the low bound of clock rate of a 10Gb MAC is 150Mhz --> 40110152Satgutier@umich.edu <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> 40210152Satgutier@umich.edu <param name="clockrate" value="350"/> 40310152Satgutier@umich.edu <param name="number_units" value="2"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port --> 40410152Satgutier@umich.edu <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> 40510152Satgutier@umich.edu <stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth --> 40610152Satgutier@umich.edu <!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate 40710152Satgutier@umich.edu the average power per nic or per channel. This is sufficent for most application. --> 40810152Satgutier@umich.edu </component> 40910152Satgutier@umich.edu<!--**********************************************************************--> 41010152Satgutier@umich.edu <component id="system.pcie" name="pcie"> 41110152Satgutier@umich.edu <!-- On chip PCIe controller, including Phy--> 41210152Satgutier@umich.edu <!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. 41310152Satgutier@umich.edu the low bound of clock rate of a PCIe per lane logic is 120Mhz --> 41410152Satgutier@umich.edu <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> 41510152Satgutier@umich.edu <param name="withPHY" value="1"/> 41610152Satgutier@umich.edu <param name="clockrate" value="350"/> 41710152Satgutier@umich.edu <param name="number_units" value="1"/> 41810152Satgutier@umich.edu <param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 --> 41910152Satgutier@umich.edu <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> 42010152Satgutier@umich.edu <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> 42110152Satgutier@umich.edu <!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate 42210152Satgutier@umich.edu the average power per pcie controller or per channel. This is sufficent for most application. --> 42310152Satgutier@umich.edu </component> 42410152Satgutier@umich.edu<!--**********************************************************************--> 42510152Satgutier@umich.edu <component id="system.flashc" name="flashc"> 42610152Satgutier@umich.edu <param name="number_flashcs" value="0"/> 42710152Satgutier@umich.edu <param name="type" value="1"/> <!-- 1: low power; 0 high performance --> 42810152Satgutier@umich.edu <param name="withPHY" value="1"/> 42910152Satgutier@umich.edu <param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S --> 43010152Satgutier@umich.edu <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> 43110152Satgutier@umich.edu <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> 43210152Satgutier@umich.edu <!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate 43310152Satgutier@umich.edu the average power per fc or per channel. This is sufficent for most application --> 43410152Satgutier@umich.edu </component> 43510152Satgutier@umich.edu<!--**********************************************************************--> 43610152Satgutier@umich.edu 43710152Satgutier@umich.edu </component> 43810152Satgutier@umich.edu</component> 439