ElectricalTimingOptimizer.cc revision 10447
110447Snilay@cs.wisc.edu#include "model/timing_graph/ElectricalTimingOptimizer.h" 210447Snilay@cs.wisc.edu 310447Snilay@cs.wisc.edu#include "model/PortInfo.h" 410447Snilay@cs.wisc.edu#include "model/ModelGen.h" 510447Snilay@cs.wisc.edu#include "model/std_cells/StdCell.h" 610447Snilay@cs.wisc.edu#include "model/std_cells/StdCellLib.h" 710447Snilay@cs.wisc.edu#include "model/timing_graph/ElectricalNet.h" 810447Snilay@cs.wisc.edu#include "model/timing_graph/ElectricalTimingTree.h" 910447Snilay@cs.wisc.edu 1010447Snilay@cs.wisc.edunamespace DSENT 1110447Snilay@cs.wisc.edu{ 1210447Snilay@cs.wisc.edu ElectricalTimingOptimizer::ElectricalTimingOptimizer(const String& instance_name_, const TechModel* tech_model_) 1310447Snilay@cs.wisc.edu : ElectricalModel(instance_name_, tech_model_), m_model_(NULL) 1410447Snilay@cs.wisc.edu {} 1510447Snilay@cs.wisc.edu 1610447Snilay@cs.wisc.edu ElectricalTimingOptimizer::~ElectricalTimingOptimizer() 1710447Snilay@cs.wisc.edu {} 1810447Snilay@cs.wisc.edu 1910447Snilay@cs.wisc.edu void ElectricalTimingOptimizer::setModel(ElectricalModel* model_) 2010447Snilay@cs.wisc.edu { 2110447Snilay@cs.wisc.edu m_model_ = model_; 2210447Snilay@cs.wisc.edu return; 2310447Snilay@cs.wisc.edu } 2410447Snilay@cs.wisc.edu 2510447Snilay@cs.wisc.edu ElectricalModel* ElectricalTimingOptimizer::getModel() 2610447Snilay@cs.wisc.edu { 2710447Snilay@cs.wisc.edu return m_model_; 2810447Snilay@cs.wisc.edu } 2910447Snilay@cs.wisc.edu 3010447Snilay@cs.wisc.edu void ElectricalTimingOptimizer::constructModel() 3110447Snilay@cs.wisc.edu { 3210447Snilay@cs.wisc.edu if(getModel() == NULL) 3310447Snilay@cs.wisc.edu { 3410447Snilay@cs.wisc.edu return; 3510447Snilay@cs.wisc.edu } 3610447Snilay@cs.wisc.edu 3710447Snilay@cs.wisc.edu const Map<PortInfo*>* port_info = getModel()->getInputs(); 3810447Snilay@cs.wisc.edu Map<PortInfo*>::ConstIterator it_begin = port_info->begin(); 3910447Snilay@cs.wisc.edu Map<PortInfo*>::ConstIterator it_end = port_info->end(); 4010447Snilay@cs.wisc.edu Map<PortInfo*>::ConstIterator it; 4110447Snilay@cs.wisc.edu 4210447Snilay@cs.wisc.edu for(it = it_begin; it != it_end; ++it) 4310447Snilay@cs.wisc.edu { 4410447Snilay@cs.wisc.edu const String& port_name = it->first; 4510447Snilay@cs.wisc.edu const PortInfo* port_info = it->second; 4610447Snilay@cs.wisc.edu StdCell* inv0 = getTechModel()->getStdCellLib()->createStdCell("INV", port_name + "Driver0"); 4710447Snilay@cs.wisc.edu inv0->construct(); 4810447Snilay@cs.wisc.edu StdCell* inv1 = getTechModel()->getStdCellLib()->createStdCell("INV", port_name + "Driver1"); 4910447Snilay@cs.wisc.edu inv1->construct(); 5010447Snilay@cs.wisc.edu 5110447Snilay@cs.wisc.edu addSubInstances(inv0, 1.0); 5210447Snilay@cs.wisc.edu addSubInstances(inv1, 1.0); 5310447Snilay@cs.wisc.edu 5410447Snilay@cs.wisc.edu createInputPort(port_name, port_info->getNetIndex()); 5510447Snilay@cs.wisc.edu createNet(port_name + "Driver0In"); 5610447Snilay@cs.wisc.edu createNet(port_name + "Driver0Out"); 5710447Snilay@cs.wisc.edu createNet(port_name + "Driver1Out"); 5810447Snilay@cs.wisc.edu assignVirtualFanin(port_name + "Driver0In", port_name); 5910447Snilay@cs.wisc.edu portConnect(inv0, "A", port_name + "Driver0In"); 6010447Snilay@cs.wisc.edu portConnect(inv0, "Y", port_name + "Driver0Out"); 6110447Snilay@cs.wisc.edu portConnect(inv1, "A", port_name + "Driver0Out"); 6210447Snilay@cs.wisc.edu portConnect(inv1, "Y", port_name + "Driver1Out"); 6310447Snilay@cs.wisc.edu 6410447Snilay@cs.wisc.edu createNet(port_name + "In", port_info->getNetIndex()); 6510447Snilay@cs.wisc.edu assignVirtualFanout(port_name + "In", port_name + "Driver1Out"); 6610447Snilay@cs.wisc.edu 6710447Snilay@cs.wisc.edu portConnect(getModel(), port_name, port_name + "In"); 6810447Snilay@cs.wisc.edu } 6910447Snilay@cs.wisc.edu 7010447Snilay@cs.wisc.edu return; 7110447Snilay@cs.wisc.edu } 7210447Snilay@cs.wisc.edu}// namespace DSENT 7310447Snilay@cs.wisc.edu 74