110448Snilay@cs.wisc.edu/* Copyright (c) 2012 Massachusetts Institute of Technology
210448Snilay@cs.wisc.edu *
310448Snilay@cs.wisc.edu * Permission is hereby granted, free of charge, to any person obtaining a copy
410448Snilay@cs.wisc.edu * of this software and associated documentation files (the "Software"), to deal
510448Snilay@cs.wisc.edu * in the Software without restriction, including without limitation the rights
610448Snilay@cs.wisc.edu * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
710448Snilay@cs.wisc.edu * copies of the Software, and to permit persons to whom the Software is
810448Snilay@cs.wisc.edu * furnished to do so, subject to the following conditions:
910448Snilay@cs.wisc.edu *
1010448Snilay@cs.wisc.edu * The above copyright notice and this permission notice shall be included in
1110448Snilay@cs.wisc.edu * all copies or substantial portions of the Software.
1210448Snilay@cs.wisc.edu *
1310448Snilay@cs.wisc.edu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1410448Snilay@cs.wisc.edu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1510448Snilay@cs.wisc.edu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
1610448Snilay@cs.wisc.edu * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1710448Snilay@cs.wisc.edu * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
1810448Snilay@cs.wisc.edu * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
1910448Snilay@cs.wisc.edu * THE SOFTWARE.
2010448Snilay@cs.wisc.edu */
2110448Snilay@cs.wisc.edu
2210447Snilay@cs.wisc.edu#include "model/timing_graph/ElectricalTimingOptimizer.h"
2310447Snilay@cs.wisc.edu
2410447Snilay@cs.wisc.edu#include "model/PortInfo.h"
2510447Snilay@cs.wisc.edu#include "model/ModelGen.h"
2610447Snilay@cs.wisc.edu#include "model/std_cells/StdCell.h"
2710447Snilay@cs.wisc.edu#include "model/std_cells/StdCellLib.h"
2810447Snilay@cs.wisc.edu#include "model/timing_graph/ElectricalNet.h"
2910447Snilay@cs.wisc.edu#include "model/timing_graph/ElectricalTimingTree.h"
3010447Snilay@cs.wisc.edu
3110447Snilay@cs.wisc.edunamespace DSENT
3210447Snilay@cs.wisc.edu{
3310447Snilay@cs.wisc.edu    ElectricalTimingOptimizer::ElectricalTimingOptimizer(const String& instance_name_, const TechModel* tech_model_)
3410447Snilay@cs.wisc.edu        : ElectricalModel(instance_name_, tech_model_), m_model_(NULL)
3510447Snilay@cs.wisc.edu    {}
3610447Snilay@cs.wisc.edu
3710447Snilay@cs.wisc.edu    ElectricalTimingOptimizer::~ElectricalTimingOptimizer()
3810447Snilay@cs.wisc.edu    {}
3910447Snilay@cs.wisc.edu
4010447Snilay@cs.wisc.edu    void ElectricalTimingOptimizer::setModel(ElectricalModel* model_)
4110447Snilay@cs.wisc.edu    {
4210447Snilay@cs.wisc.edu        m_model_ = model_;
4310447Snilay@cs.wisc.edu        return;
4410447Snilay@cs.wisc.edu    }
4510447Snilay@cs.wisc.edu
4610447Snilay@cs.wisc.edu    ElectricalModel* ElectricalTimingOptimizer::getModel()
4710447Snilay@cs.wisc.edu    {
4810447Snilay@cs.wisc.edu        return m_model_;
4910447Snilay@cs.wisc.edu    }
5010447Snilay@cs.wisc.edu
5110447Snilay@cs.wisc.edu    void ElectricalTimingOptimizer::constructModel()
5210447Snilay@cs.wisc.edu    {
5310447Snilay@cs.wisc.edu        if(getModel() == NULL)
5410447Snilay@cs.wisc.edu        {
5510447Snilay@cs.wisc.edu            return;
5610447Snilay@cs.wisc.edu        }
5710447Snilay@cs.wisc.edu
5810447Snilay@cs.wisc.edu        const Map<PortInfo*>* port_info = getModel()->getInputs();
5910447Snilay@cs.wisc.edu        Map<PortInfo*>::ConstIterator it_begin = port_info->begin();
6010447Snilay@cs.wisc.edu        Map<PortInfo*>::ConstIterator it_end = port_info->end();
6110447Snilay@cs.wisc.edu        Map<PortInfo*>::ConstIterator it;
6210447Snilay@cs.wisc.edu
6310447Snilay@cs.wisc.edu        for(it = it_begin; it != it_end; ++it)
6410447Snilay@cs.wisc.edu        {
6510447Snilay@cs.wisc.edu            const String& port_name = it->first;
6610447Snilay@cs.wisc.edu            const PortInfo* port_info = it->second;
6710447Snilay@cs.wisc.edu            StdCell* inv0 = getTechModel()->getStdCellLib()->createStdCell("INV", port_name + "Driver0");
6810447Snilay@cs.wisc.edu            inv0->construct();
6910447Snilay@cs.wisc.edu            StdCell* inv1 = getTechModel()->getStdCellLib()->createStdCell("INV", port_name + "Driver1");
7010447Snilay@cs.wisc.edu            inv1->construct();
7110447Snilay@cs.wisc.edu
7210447Snilay@cs.wisc.edu            addSubInstances(inv0, 1.0);
7310447Snilay@cs.wisc.edu            addSubInstances(inv1, 1.0);
7410447Snilay@cs.wisc.edu
7510447Snilay@cs.wisc.edu            createInputPort(port_name, port_info->getNetIndex());
7610447Snilay@cs.wisc.edu            createNet(port_name + "Driver0In");
7710447Snilay@cs.wisc.edu            createNet(port_name + "Driver0Out");
7810447Snilay@cs.wisc.edu            createNet(port_name + "Driver1Out");
7910447Snilay@cs.wisc.edu            assignVirtualFanin(port_name + "Driver0In", port_name);
8010447Snilay@cs.wisc.edu            portConnect(inv0, "A", port_name + "Driver0In");
8110447Snilay@cs.wisc.edu            portConnect(inv0, "Y", port_name + "Driver0Out");
8210447Snilay@cs.wisc.edu            portConnect(inv1, "A", port_name + "Driver0Out");
8310447Snilay@cs.wisc.edu            portConnect(inv1, "Y", port_name + "Driver1Out");
8410447Snilay@cs.wisc.edu
8510447Snilay@cs.wisc.edu            createNet(port_name + "In", port_info->getNetIndex());
8610447Snilay@cs.wisc.edu            assignVirtualFanout(port_name + "In", port_name + "Driver1Out");
8710447Snilay@cs.wisc.edu
8810447Snilay@cs.wisc.edu            portConnect(getModel(), port_name, port_name + "In");
8910447Snilay@cs.wisc.edu        }
9010447Snilay@cs.wisc.edu
9110447Snilay@cs.wisc.edu        return;
9210447Snilay@cs.wisc.edu    }
9310447Snilay@cs.wisc.edu}// namespace DSENT
9410447Snilay@cs.wisc.edu
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