RouterInputPort.cc revision 10447
110447Snilay@cs.wisc.edu#include "model/electrical/router/RouterInputPort.h" 210447Snilay@cs.wisc.edu 310447Snilay@cs.wisc.edu#include <cmath> 410447Snilay@cs.wisc.edu#include <vector> 510447Snilay@cs.wisc.edu 610447Snilay@cs.wisc.edu#include "model/PortInfo.h" 710447Snilay@cs.wisc.edu#include "model/EventInfo.h" 810447Snilay@cs.wisc.edu#include "model/TransitionInfo.h" 910447Snilay@cs.wisc.edu#include "model/ModelGen.h" 1010447Snilay@cs.wisc.edu#include "model/std_cells/StdCellLib.h" 1110447Snilay@cs.wisc.edu#include "model/std_cells/StdCell.h" 1210447Snilay@cs.wisc.edu 1310447Snilay@cs.wisc.edunamespace DSENT 1410447Snilay@cs.wisc.edu{ 1510447Snilay@cs.wisc.edu using std::ceil; 1610447Snilay@cs.wisc.edu using std::vector; 1710447Snilay@cs.wisc.edu using LibUtil::castStringVector; 1810447Snilay@cs.wisc.edu 1910447Snilay@cs.wisc.edu RouterInputPort::RouterInputPort(const String& instance_name_, const TechModel* tech_model_) 2010447Snilay@cs.wisc.edu : ElectricalModel(instance_name_, tech_model_) 2110447Snilay@cs.wisc.edu { 2210447Snilay@cs.wisc.edu initParameters(); 2310447Snilay@cs.wisc.edu initProperties(); 2410447Snilay@cs.wisc.edu } 2510447Snilay@cs.wisc.edu 2610447Snilay@cs.wisc.edu RouterInputPort::~RouterInputPort() 2710447Snilay@cs.wisc.edu {} 2810447Snilay@cs.wisc.edu 2910447Snilay@cs.wisc.edu void RouterInputPort::initParameters() 3010447Snilay@cs.wisc.edu { 3110447Snilay@cs.wisc.edu addParameterName("NumberVirtualNetworks"); 3210447Snilay@cs.wisc.edu addParameterName("NumberVirtualChannelsPerVirtualNetwork"); 3310447Snilay@cs.wisc.edu addParameterName("NumberBuffersPerVirtualChannel"); 3410447Snilay@cs.wisc.edu addParameterName("NumberBitsPerFlit"); 3510447Snilay@cs.wisc.edu addParameterName("BufferModel"); 3610447Snilay@cs.wisc.edu return; 3710447Snilay@cs.wisc.edu } 3810447Snilay@cs.wisc.edu 3910447Snilay@cs.wisc.edu void RouterInputPort::initProperties() 4010447Snilay@cs.wisc.edu { 4110447Snilay@cs.wisc.edu return; 4210447Snilay@cs.wisc.edu } 4310447Snilay@cs.wisc.edu 4410447Snilay@cs.wisc.edu RouterInputPort* RouterInputPort::clone() const 4510447Snilay@cs.wisc.edu { 4610447Snilay@cs.wisc.edu // TODO 4710447Snilay@cs.wisc.edu return NULL; 4810447Snilay@cs.wisc.edu } 4910447Snilay@cs.wisc.edu 5010447Snilay@cs.wisc.edu void RouterInputPort::constructModel() 5110447Snilay@cs.wisc.edu { 5210447Snilay@cs.wisc.edu // Get parameters 5310447Snilay@cs.wisc.edu unsigned int number_vns = getParameter("NumberVirtualNetworks").toUInt(); 5410447Snilay@cs.wisc.edu const vector<unsigned int>& number_vcs_per_vn_vector = castStringVector<unsigned int>(getParameter("NumberVirtualChannelsPerVirtualNetwork").split("[,]")); 5510447Snilay@cs.wisc.edu const vector<unsigned int>& number_bufs_per_vc_vector = castStringVector<unsigned int>(getParameter("NumberBuffersPerVirtualChannel").split("[,]")); 5610447Snilay@cs.wisc.edu unsigned int number_bits_per_flit = getParameter("NumberBitsPerFlit").toUInt(); 5710447Snilay@cs.wisc.edu const String& buffer_model = getParameter("BufferModel"); 5810447Snilay@cs.wisc.edu 5910447Snilay@cs.wisc.edu ASSERT(number_vns > 0, "[Error] " + getInstanceName() + 6010447Snilay@cs.wisc.edu " -> Number of virtual networks must be > 0!"); 6110447Snilay@cs.wisc.edu ASSERT(number_vcs_per_vn_vector.size() == number_vns, "[Error] " + getInstanceName() + 6210447Snilay@cs.wisc.edu " -> Expecting " + (String)number_vns + " number of vcs, got " + 6310447Snilay@cs.wisc.edu getParameter("NumberVirtualChannelsPerVirtualNetwork")); 6410447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_vns; ++i) 6510447Snilay@cs.wisc.edu { 6610447Snilay@cs.wisc.edu ASSERT(number_vcs_per_vn_vector[i] > 0, "[Error] " + getInstanceName() + 6710447Snilay@cs.wisc.edu " -> Number of virtual channels per virtual network must be > 0!"); 6810447Snilay@cs.wisc.edu } 6910447Snilay@cs.wisc.edu ASSERT(number_bufs_per_vc_vector.size() == number_vns, "[Error] " + getInstanceName() + 7010447Snilay@cs.wisc.edu " -> Expecting " + (String)number_vns + " number of bufs per vc, got " + 7110447Snilay@cs.wisc.edu getParameter("NumberBuffersPerVirtualChannel")); 7210447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_vns; ++i) 7310447Snilay@cs.wisc.edu { 7410447Snilay@cs.wisc.edu ASSERT(number_bufs_per_vc_vector[i] > 0, "[Error] " + getInstanceName() + 7510447Snilay@cs.wisc.edu " -> Number of buffers per virtual channel must be > 0!"); 7610447Snilay@cs.wisc.edu } 7710447Snilay@cs.wisc.edu ASSERT(number_bits_per_flit > 0, "[Error] " + getInstanceName() + 7810447Snilay@cs.wisc.edu " -> Number of bits per buffer must be > 0!"); 7910447Snilay@cs.wisc.edu 8010447Snilay@cs.wisc.edu // Calculate total number of buffers needed in the RAM 8110447Snilay@cs.wisc.edu unsigned int total_number_vcs = 0; 8210447Snilay@cs.wisc.edu unsigned int total_number_bufs = 0; 8310447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_vns; ++i) 8410447Snilay@cs.wisc.edu { 8510447Snilay@cs.wisc.edu total_number_vcs += number_vcs_per_vn_vector[i]; 8610447Snilay@cs.wisc.edu total_number_bufs += number_vcs_per_vn_vector[i] * number_bufs_per_vc_vector[i]; 8710447Snilay@cs.wisc.edu } 8810447Snilay@cs.wisc.edu unsigned int number_addr_bits = (unsigned int)ceil(log2(total_number_bufs)); 8910447Snilay@cs.wisc.edu 9010447Snilay@cs.wisc.edu getGenProperties()->set("TotalNumberVirtualChannels", total_number_vcs); 9110447Snilay@cs.wisc.edu getGenProperties()->set("TotalNumberBuffers", total_number_bufs); 9210447Snilay@cs.wisc.edu getGenProperties()->set("NumberAddressBits", number_addr_bits); 9310447Snilay@cs.wisc.edu getGenProperties()->set("NumberOutputs", 1); 9410447Snilay@cs.wisc.edu 9510447Snilay@cs.wisc.edu createInputPort("CK"); 9610447Snilay@cs.wisc.edu createInputPort("FlitIn", makeNetIndex(0, number_bits_per_flit-1)); 9710447Snilay@cs.wisc.edu createOutputPort("FlitOut", makeNetIndex(0, number_bits_per_flit-1)); 9810447Snilay@cs.wisc.edu 9910447Snilay@cs.wisc.edu // Create energy, power, and area results 10010447Snilay@cs.wisc.edu createElectricalResults(); 10110447Snilay@cs.wisc.edu getEventInfo("Idle")->setStaticTransitionInfos(); 10210447Snilay@cs.wisc.edu getEventInfo("Idle")->setTransitionInfo("CK", TransitionInfo(0.0, 1.0, 0.0)); 10310447Snilay@cs.wisc.edu 10410447Snilay@cs.wisc.edu addEventResult(new Result("ReadBuffer")); 10510447Snilay@cs.wisc.edu addEventResult(new Result("WriteBuffer")); 10610447Snilay@cs.wisc.edu 10710447Snilay@cs.wisc.edu // Init RAM 10810447Snilay@cs.wisc.edu const String& ram_name = "RAM"; 10910447Snilay@cs.wisc.edu ElectricalModel* ram = ModelGen::createRAM(buffer_model, ram_name, getTechModel()); 11010447Snilay@cs.wisc.edu ram->setParameter("NumberEntries", total_number_bufs); 11110447Snilay@cs.wisc.edu ram->setParameter("NumberBits", number_bits_per_flit); 11210447Snilay@cs.wisc.edu ram->construct(); 11310447Snilay@cs.wisc.edu 11410447Snilay@cs.wisc.edu // Init DFF for read address 11510447Snilay@cs.wisc.edu vector<String> rd_addr_dff_names(number_addr_bits, ""); 11610447Snilay@cs.wisc.edu vector<StdCell*> rd_addr_dffs(number_addr_bits, NULL); 11710447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 11810447Snilay@cs.wisc.edu { 11910447Snilay@cs.wisc.edu rd_addr_dff_names[i] = "RDAddr_DFF" + (String)i; 12010447Snilay@cs.wisc.edu rd_addr_dffs[i] = getTechModel()->getStdCellLib()->createStdCell("DFFQ", rd_addr_dff_names[i]); 12110447Snilay@cs.wisc.edu rd_addr_dffs[i]->construct(); 12210447Snilay@cs.wisc.edu } 12310447Snilay@cs.wisc.edu 12410447Snilay@cs.wisc.edu // Connect RDAddr_DFFs 12510447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 12610447Snilay@cs.wisc.edu { 12710447Snilay@cs.wisc.edu createNet("RDAddr_DFF_Out" + (String)i); 12810447Snilay@cs.wisc.edu 12910447Snilay@cs.wisc.edu portConnect(rd_addr_dffs[i], "CK", "CK"); 13010447Snilay@cs.wisc.edu portConnect(rd_addr_dffs[i], "Q", "RDAddr_DFF_Out" + (String)i); 13110447Snilay@cs.wisc.edu } 13210447Snilay@cs.wisc.edu 13310447Snilay@cs.wisc.edu // Connect RAM 13410447Snilay@cs.wisc.edu portConnect(ram, "In", "FlitIn"); 13510447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 13610447Snilay@cs.wisc.edu { 13710447Snilay@cs.wisc.edu portConnect(ram, "WRAddr" + (String)i, "FlitIn", makeNetIndex(i)); 13810447Snilay@cs.wisc.edu portConnect(ram, "RDAddr" + (String)i, "RDAddr_DFF_Out" + (String)i); 13910447Snilay@cs.wisc.edu } 14010447Snilay@cs.wisc.edu portConnect(ram, "WE", "FlitIn", makeNetIndex(number_bits_per_flit-1)); 14110447Snilay@cs.wisc.edu portConnect(ram, "CK", "CK"); 14210447Snilay@cs.wisc.edu portConnect(ram, "Out", "FlitOut"); 14310447Snilay@cs.wisc.edu 14410447Snilay@cs.wisc.edu // Add area, power, event results 14510447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 14610447Snilay@cs.wisc.edu { 14710447Snilay@cs.wisc.edu addSubInstances(rd_addr_dffs[i], number_addr_bits); 14810447Snilay@cs.wisc.edu addElectricalSubResults(rd_addr_dffs[i], number_addr_bits); 14910447Snilay@cs.wisc.edu } 15010447Snilay@cs.wisc.edu addSubInstances(ram, 1.0); 15110447Snilay@cs.wisc.edu addElectricalSubResults(ram, 1.0); 15210447Snilay@cs.wisc.edu 15310447Snilay@cs.wisc.edu getEventResult("WriteBuffer")->addSubResult(ram->getEventResult("Write"), ram_name, 1.0); 15410447Snilay@cs.wisc.edu 15510447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 15610447Snilay@cs.wisc.edu { 15710447Snilay@cs.wisc.edu getEventResult("ReadBuffer")->addSubResult(rd_addr_dffs[i]->getEventResult("DFFD"), rd_addr_dff_names[i], number_addr_bits); 15810447Snilay@cs.wisc.edu getEventResult("ReadBuffer")->addSubResult(rd_addr_dffs[i]->getEventResult("DFFQ"), rd_addr_dff_names[i], number_addr_bits); 15910447Snilay@cs.wisc.edu getEventResult("ReadBuffer")->addSubResult(rd_addr_dffs[i]->getEventResult("CK"), rd_addr_dff_names[i], number_addr_bits); 16010447Snilay@cs.wisc.edu } 16110447Snilay@cs.wisc.edu getEventResult("ReadBuffer")->addSubResult(ram->getEventResult("Read"), ram_name, 1.0); 16210447Snilay@cs.wisc.edu 16310447Snilay@cs.wisc.edu return; 16410447Snilay@cs.wisc.edu } 16510447Snilay@cs.wisc.edu 16610447Snilay@cs.wisc.edu void RouterInputPort::propagateTransitionInfo() 16710447Snilay@cs.wisc.edu { 16810447Snilay@cs.wisc.edu // Update probability and activity 16910447Snilay@cs.wisc.edu unsigned int number_addr_bits = getGenProperties()->get("NumberAddressBits").toUInt(); 17010447Snilay@cs.wisc.edu 17110447Snilay@cs.wisc.edu vector<ElectricalModel*> rd_addr_dffs(number_addr_bits, NULL); 17210447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 17310447Snilay@cs.wisc.edu { 17410447Snilay@cs.wisc.edu rd_addr_dffs[i] = (ElectricalModel*)getSubInstance("RDAddr_DFF" + (String)i); 17510447Snilay@cs.wisc.edu assignPortTransitionInfo(rd_addr_dffs[i], "D", TransitionInfo()); 17610447Snilay@cs.wisc.edu propagatePortTransitionInfo(rd_addr_dffs[i], "CK", "CK"); 17710447Snilay@cs.wisc.edu rd_addr_dffs[i]->use(); 17810447Snilay@cs.wisc.edu } 17910447Snilay@cs.wisc.edu 18010447Snilay@cs.wisc.edu ElectricalModel* ram = (ElectricalModel*)getSubInstance("RAM"); 18110447Snilay@cs.wisc.edu 18210447Snilay@cs.wisc.edu // Setup default transition info 18310447Snilay@cs.wisc.edu const String& current_event = getGenProperties()->get("UseModelEvent"); 18410447Snilay@cs.wisc.edu if(current_event != "Idle") 18510447Snilay@cs.wisc.edu { 18610447Snilay@cs.wisc.edu propagatePortTransitionInfo(ram, "In", "FlitIn"); 18710447Snilay@cs.wisc.edu propagatePortTransitionInfo(ram, "CK", "CK"); 18810447Snilay@cs.wisc.edu assignPortTransitionInfo(ram, "WE", TransitionInfo(0.0, 0.0, 1.0)); 18910447Snilay@cs.wisc.edu for(unsigned int i = 0; i < number_addr_bits; ++i) 19010447Snilay@cs.wisc.edu { 19110447Snilay@cs.wisc.edu assignPortTransitionInfo(ram, "WRAddr" + (String)i, TransitionInfo(0.25, 0.25, 0.25)); 19210447Snilay@cs.wisc.edu assignPortTransitionInfo(ram, "RDAddr" + (String)i, TransitionInfo(0.25, 0.25, 0.25)); 19310447Snilay@cs.wisc.edu } 19410447Snilay@cs.wisc.edu } 19510447Snilay@cs.wisc.edu ram->use(); 19610447Snilay@cs.wisc.edu // Set output probability 19710447Snilay@cs.wisc.edu propagatePortTransitionInfo("FlitOut", ram, "Out"); 19810447Snilay@cs.wisc.edu return; 19910447Snilay@cs.wisc.edu } 20010447Snilay@cs.wisc.edu} // namespace DSENT 20110447Snilay@cs.wisc.edu 202