MemorySpecification.h revision 10428
110428Sandreas.hansson@arm.com/* 210428Sandreas.hansson@arm.com * Copyright (c) 2012-2014, TU Delft 310428Sandreas.hansson@arm.com * Copyright (c) 2012-2014, TU Eindhoven 410428Sandreas.hansson@arm.com * Copyright (c) 2012-2014, TU Kaiserslautern 510428Sandreas.hansson@arm.com * All rights reserved. 610428Sandreas.hansson@arm.com * 710428Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 810428Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 910428Sandreas.hansson@arm.com * met: 1010428Sandreas.hansson@arm.com * 1110428Sandreas.hansson@arm.com * 1. Redistributions of source code must retain the above copyright 1210428Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer. 1310428Sandreas.hansson@arm.com * 1410428Sandreas.hansson@arm.com * 2. Redistributions in binary form must reproduce the above copyright 1510428Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 1610428Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution. 1710428Sandreas.hansson@arm.com * 1810428Sandreas.hansson@arm.com * 3. Neither the name of the copyright holder nor the names of its 1910428Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 2010428Sandreas.hansson@arm.com * this software without specific prior written permission. 2110428Sandreas.hansson@arm.com * 2210428Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 2310428Sandreas.hansson@arm.com * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2410428Sandreas.hansson@arm.com * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 2510428Sandreas.hansson@arm.com * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2610428Sandreas.hansson@arm.com * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2710428Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 2810428Sandreas.hansson@arm.com * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 2910428Sandreas.hansson@arm.com * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 3010428Sandreas.hansson@arm.com * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 3110428Sandreas.hansson@arm.com * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 3210428Sandreas.hansson@arm.com * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3310428Sandreas.hansson@arm.com * 3410428Sandreas.hansson@arm.com * Authors: Karthik Chandrasekar 3510428Sandreas.hansson@arm.com * 3610428Sandreas.hansson@arm.com */ 3710428Sandreas.hansson@arm.com 3810428Sandreas.hansson@arm.com#ifndef TOOLS_MEMORY_SPECIFICATION_H 3910428Sandreas.hansson@arm.com#define TOOLS_MEMORY_SPECIFICATION_H 4010428Sandreas.hansson@arm.com 4110428Sandreas.hansson@arm.com#include <cassert> 4210428Sandreas.hansson@arm.com#include <string> 4310428Sandreas.hansson@arm.com 4410428Sandreas.hansson@arm.com#include "MemArchitectureSpec.h" 4510428Sandreas.hansson@arm.com#include "MemTimingSpec.h" 4610428Sandreas.hansson@arm.com#include "MemPowerSpec.h" 4710428Sandreas.hansson@arm.com#include "Parametrisable.h" 4810428Sandreas.hansson@arm.com 4910428Sandreas.hansson@arm.com 5010428Sandreas.hansson@arm.comnamespace Data { 5110428Sandreas.hansson@arm.com// Supported memory types 5210428Sandreas.hansson@arm.comclass MemoryType { 5310428Sandreas.hansson@arm.com public: 5410428Sandreas.hansson@arm.com enum MemoryType_t { 5510428Sandreas.hansson@arm.com DDR2 = 0, 5610428Sandreas.hansson@arm.com DDR3, 5710428Sandreas.hansson@arm.com DDR4, 5810428Sandreas.hansson@arm.com LPDDR, 5910428Sandreas.hansson@arm.com LPDDR2, 6010428Sandreas.hansson@arm.com LPDDR3, 6110428Sandreas.hansson@arm.com WIDEIO_SDR, 6210428Sandreas.hansson@arm.com MEMORY_TYPE_INVALID 6310428Sandreas.hansson@arm.com }; 6410428Sandreas.hansson@arm.com 6510428Sandreas.hansson@arm.com MemoryType(MemoryType_t _val) : 6610428Sandreas.hansson@arm.com val(_val) 6710428Sandreas.hansson@arm.com { 6810428Sandreas.hansson@arm.com } 6910428Sandreas.hansson@arm.com 7010428Sandreas.hansson@arm.com MemoryType() : 7110428Sandreas.hansson@arm.com val(MEMORY_TYPE_INVALID) 7210428Sandreas.hansson@arm.com { 7310428Sandreas.hansson@arm.com } 7410428Sandreas.hansson@arm.com 7510428Sandreas.hansson@arm.com MemoryType(const std::string& _val) : 7610428Sandreas.hansson@arm.com val(MEMORY_TYPE_INVALID) 7710428Sandreas.hansson@arm.com { 7810428Sandreas.hansson@arm.com if (_val == "DDR2") { 7910428Sandreas.hansson@arm.com val = DDR2; 8010428Sandreas.hansson@arm.com } else if (_val == "DDR3") { 8110428Sandreas.hansson@arm.com val = DDR3; 8210428Sandreas.hansson@arm.com } else if (_val == "DDR4") { 8310428Sandreas.hansson@arm.com val = DDR4; 8410428Sandreas.hansson@arm.com } else if (_val == "LPDDR") { 8510428Sandreas.hansson@arm.com val = LPDDR; 8610428Sandreas.hansson@arm.com } else if (_val == "LPDDR2") { 8710428Sandreas.hansson@arm.com val = LPDDR2; 8810428Sandreas.hansson@arm.com } else if (_val == "LPDDR3") { 8910428Sandreas.hansson@arm.com val = LPDDR3; 9010428Sandreas.hansson@arm.com } else if (_val == "WIDEIO_SDR") { 9110428Sandreas.hansson@arm.com val = WIDEIO_SDR; 9210428Sandreas.hansson@arm.com } 9310428Sandreas.hansson@arm.com assert("Unknown memory type." && val != MEMORY_TYPE_INVALID); 9410428Sandreas.hansson@arm.com } 9510428Sandreas.hansson@arm.com 9610428Sandreas.hansson@arm.com bool isLPDDRFamily() const 9710428Sandreas.hansson@arm.com { 9810428Sandreas.hansson@arm.com return val == LPDDR || 9910428Sandreas.hansson@arm.com val == LPDDR2 || 10010428Sandreas.hansson@arm.com val == LPDDR3 || 10110428Sandreas.hansson@arm.com val == WIDEIO_SDR; 10210428Sandreas.hansson@arm.com } 10310428Sandreas.hansson@arm.com 10410428Sandreas.hansson@arm.com bool hasTwoVoltageDomains() const 10510428Sandreas.hansson@arm.com { 10610428Sandreas.hansson@arm.com return val == LPDDR || 10710428Sandreas.hansson@arm.com val == LPDDR2 || 10810428Sandreas.hansson@arm.com val == LPDDR3 || 10910428Sandreas.hansson@arm.com val == WIDEIO_SDR; 11010428Sandreas.hansson@arm.com } 11110428Sandreas.hansson@arm.com 11210428Sandreas.hansson@arm.com bool isDDRFamily() const 11310428Sandreas.hansson@arm.com { 11410428Sandreas.hansson@arm.com return val == DDR2 || 11510428Sandreas.hansson@arm.com val == DDR3 || 11610428Sandreas.hansson@arm.com val == DDR4; 11710428Sandreas.hansson@arm.com } 11810428Sandreas.hansson@arm.com 11910428Sandreas.hansson@arm.com bool hasDll() const 12010428Sandreas.hansson@arm.com { 12110428Sandreas.hansson@arm.com return val == DDR2 || 12210428Sandreas.hansson@arm.com val == DDR3 || 12310428Sandreas.hansson@arm.com val == DDR4; 12410428Sandreas.hansson@arm.com } 12510428Sandreas.hansson@arm.com 12610428Sandreas.hansson@arm.com bool hasTermination() const 12710428Sandreas.hansson@arm.com { 12810428Sandreas.hansson@arm.com return val == DDR2 || 12910428Sandreas.hansson@arm.com val == DDR3 || 13010428Sandreas.hansson@arm.com val == DDR4; 13110428Sandreas.hansson@arm.com } 13210428Sandreas.hansson@arm.com 13310428Sandreas.hansson@arm.com double getCapacitance() const 13410428Sandreas.hansson@arm.com { 13510428Sandreas.hansson@arm.com // LPDDR/2/3 and DDR memories only have IO Power (no ODT) 13610428Sandreas.hansson@arm.com // Conservative estimates based on Micron Mobile LPDDR2 Power Calculator 13710428Sandreas.hansson@arm.com // LPDDR/2/3 IO Capacitance in mF 13810428Sandreas.hansson@arm.com if (val == LPDDR) { 13910428Sandreas.hansson@arm.com return 0.0000000045; 14010428Sandreas.hansson@arm.com } else if (val == LPDDR2) { 14110428Sandreas.hansson@arm.com return 0.0000000025; 14210428Sandreas.hansson@arm.com } else if (val == LPDDR3) { 14310428Sandreas.hansson@arm.com return 0.0000000018; 14410428Sandreas.hansson@arm.com } else { 14510428Sandreas.hansson@arm.com return 0.0; 14610428Sandreas.hansson@arm.com } 14710428Sandreas.hansson@arm.com } 14810428Sandreas.hansson@arm.com 14910428Sandreas.hansson@arm.com double getIoPower() const 15010428Sandreas.hansson@arm.com { 15110428Sandreas.hansson@arm.com if (val == DDR2) { 15210428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR2 Power Calculator 15310428Sandreas.hansson@arm.com return 1.5; // in mW 15410428Sandreas.hansson@arm.com } else if (val == DDR3) { 15510428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR3 Power Calculator 15610428Sandreas.hansson@arm.com return 4.6; // in mW 15710428Sandreas.hansson@arm.com } else if (val == DDR4) { 15810428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR3 Power Calculator 15910428Sandreas.hansson@arm.com // using available termination resistance values from Micron DDR4 Datasheets 16010428Sandreas.hansson@arm.com return 3.7; // in mW 16110428Sandreas.hansson@arm.com } else { 16210428Sandreas.hansson@arm.com return 0.0; 16310428Sandreas.hansson@arm.com } 16410428Sandreas.hansson@arm.com } 16510428Sandreas.hansson@arm.com 16610428Sandreas.hansson@arm.com double getWrOdtPower() const 16710428Sandreas.hansson@arm.com { 16810428Sandreas.hansson@arm.com if (val == DDR2) { 16910428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR2 Power Calculator 17010428Sandreas.hansson@arm.com return 8.2; // in mW 17110428Sandreas.hansson@arm.com } else if (val == DDR3) { 17210428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR3 Power Calculator 17310428Sandreas.hansson@arm.com return 21.2; // in mW 17410428Sandreas.hansson@arm.com } else if (val == DDR4) { 17510428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR3 Power Calculator 17610428Sandreas.hansson@arm.com // using available termination resistance values from Micron DDR4 Datasheets 17710428Sandreas.hansson@arm.com return 17.0; // in mW 17810428Sandreas.hansson@arm.com } else { 17910428Sandreas.hansson@arm.com return 0.0; 18010428Sandreas.hansson@arm.com } 18110428Sandreas.hansson@arm.com } 18210428Sandreas.hansson@arm.com 18310428Sandreas.hansson@arm.com double getTermRdPower() const 18410428Sandreas.hansson@arm.com { 18510428Sandreas.hansson@arm.com if (val == DDR2) { 18610428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR2 Power Calculator 18710428Sandreas.hansson@arm.com return 13.1; // in mW 18810428Sandreas.hansson@arm.com } else if (val == DDR3) { 18910428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR3 Power Calculator 19010428Sandreas.hansson@arm.com return 15.5; // in mW 19110428Sandreas.hansson@arm.com } else if (val == DDR4) { 19210428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR3 Power Calculator 19310428Sandreas.hansson@arm.com // using available termination resistance values from Micron DDR4 Datasheets 19410428Sandreas.hansson@arm.com return 12.4; // in mW 19510428Sandreas.hansson@arm.com } else { 19610428Sandreas.hansson@arm.com return 0.0; 19710428Sandreas.hansson@arm.com } 19810428Sandreas.hansson@arm.com } 19910428Sandreas.hansson@arm.com 20010428Sandreas.hansson@arm.com double getTermWrPower() const 20110428Sandreas.hansson@arm.com { 20210428Sandreas.hansson@arm.com if (val == DDR2) { 20310428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR2 Power Calculator 20410428Sandreas.hansson@arm.com return 14.6; // in mW 20510428Sandreas.hansson@arm.com } else if (val == DDR3) { 20610428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR3 Power Calculator 20710428Sandreas.hansson@arm.com return 15.4; // in mW 20810428Sandreas.hansson@arm.com } else if (val == DDR4) { 20910428Sandreas.hansson@arm.com // Conservative estimates based on Micron DDR3 Power Calculator 21010428Sandreas.hansson@arm.com // using available termination resistance values from Micron DDR4 Datasheets 21110428Sandreas.hansson@arm.com return 12.3; // in mW 21210428Sandreas.hansson@arm.com } else { 21310428Sandreas.hansson@arm.com return 0.0; 21410428Sandreas.hansson@arm.com } 21510428Sandreas.hansson@arm.com } 21610428Sandreas.hansson@arm.com 21710428Sandreas.hansson@arm.com operator MemoryType_t() const { 21810428Sandreas.hansson@arm.com return val; 21910428Sandreas.hansson@arm.com } 22010428Sandreas.hansson@arm.com 22110428Sandreas.hansson@arm.com private: 22210428Sandreas.hansson@arm.com MemoryType_t val; 22310428Sandreas.hansson@arm.com}; 22410428Sandreas.hansson@arm.com 22510428Sandreas.hansson@arm.comclass MemorySpecification : public virtual Parametrisable { 22610428Sandreas.hansson@arm.com public: 22710428Sandreas.hansson@arm.com std::string id; 22810428Sandreas.hansson@arm.com MemoryType memoryType; 22910428Sandreas.hansson@arm.com 23010428Sandreas.hansson@arm.com MemArchitectureSpec memArchSpec; 23110428Sandreas.hansson@arm.com MemTimingSpec memTimingSpec; 23210428Sandreas.hansson@arm.com MemPowerSpec memPowerSpec; 23310428Sandreas.hansson@arm.com 23410428Sandreas.hansson@arm.com void processParameters(); 23510428Sandreas.hansson@arm.com 23610428Sandreas.hansson@arm.com static MemorySpecification getMemSpecFromXML(const std::string& id); 23710428Sandreas.hansson@arm.com}; 23810428Sandreas.hansson@arm.com} // namespace Data 23910428Sandreas.hansson@arm.com#endif // ifndef TOOLS_MEMORY_SPECIFICATION_H 240