README.md revision 12266
110428Sandreas.hansson@arm.com# DRAM Power Model (DRAMPower) 210428Sandreas.hansson@arm.com[![Build Status](https://travis-ci.org/ravenrd/DRAMPower.svg?branch=master)](https://travis-ci.org/ravenrd/DRAMPower) 310428Sandreas.hansson@arm.com[![Coverage Status](https://coveralls.io/repos/ravenrd/DRAMPower/badge.png?branch=master)](https://coveralls.io/r/ravenrd/DRAMPower?branch=master) 410428Sandreas.hansson@arm.com## 0. Releases 510428Sandreas.hansson@arm.com 610428Sandreas.hansson@arm.comThe last official release can be found here: 710428Sandreas.hansson@arm.comhttps://github.com/ravenrd/DRAMPower/releases/tag/4.0 810428Sandreas.hansson@arm.com 910428Sandreas.hansson@arm.comThe master branch of the repository should be regarded as the bleeding-edge version, which has all the latest features, but also all the latest bugs. Use at your own discretion. 1010428Sandreas.hansson@arm.com 1110428Sandreas.hansson@arm.com## 1. Installation 1210428Sandreas.hansson@arm.com 1312266Sradhika.jagtap@arm.comClone the repository, or download the zip file of the release you would like to use. The source code is available in src folder. [drampower.cc](src/cli/drampower.cc) file gives the user interface, where the user can specify the memory to be employed and the command/transaction trace to be analyzed. To build, use: 1410428Sandreas.hansson@arm.com```bash 1510428Sandreas.hansson@arm.commake -j4 1610428Sandreas.hansson@arm.com``` 1710428Sandreas.hansson@arm.comThis command will download a set of trace files from https://github.com/Sv3n/DRAMPowerTraces which can be used as test input for the tool. 1810428Sandreas.hansson@arm.com 1910428Sandreas.hansson@arm.com## 2. Required Packages 2010428Sandreas.hansson@arm.com 2110428Sandreas.hansson@arm.comThe tool was verified on Ubuntu 14.04 using: 2210428Sandreas.hansson@arm.com 2310428Sandreas.hansson@arm.com * xerces-c (libxerces-c-dev) - v3.1 with Xerces development package 2410428Sandreas.hansson@arm.com * gcc - v4.4.3 2510428Sandreas.hansson@arm.com 2610428Sandreas.hansson@arm.com## 3. Directory Structure 2710428Sandreas.hansson@arm.com * src/: contains the source code of the DRAMPower tool that covers the power model, the command scheduler and the trace analysis tool. 2810428Sandreas.hansson@arm.com * memspecs/ : contains the memory specification XMLs, which give the architectural, timing and current/voltage details for different DRAM memories. 2910428Sandreas.hansson@arm.com * traces/ : contains 4 sample DRAM transaction traces and 1 sample command trace (after the installation / compilation) 3010428Sandreas.hansson@arm.com * test/ : contains test script and reference output 3110428Sandreas.hansson@arm.com 3210428Sandreas.hansson@arm.com## 4. Trace Specification 3310428Sandreas.hansson@arm.com### Command Traces 3410428Sandreas.hansson@arm.comIf the command-level interface is being used, a command trace can be logged in a file. 3510428Sandreas.hansson@arm.comAn example is given in ```traces/commands.trace``` 3610428Sandreas.hansson@arm.com 3710428Sandreas.hansson@arm.comThe format it uses is: ```<timestamp>,<command>,<bank>```. 3810428Sandreas.hansson@arm.comFor example, "500,ACT,2", where ACT is the command and 2 is the bank. Timestamp is in clock cycles (cc), the list of supported commands is 3912266Sradhika.jagtap@arm.commentioned in [MemCommand.h](src/MemCommand.h) and the bank is the target bank number. For non-bank-specific commands, bank can be set to 0. Rank need not be 4010428Sandreas.hansson@arm.comspecified. The timing correctness of the trace is not verified by the tool and is assumed to be accurate. However, warning messages are provided, to identify if the memory or bank state is inconsistent in the trace. A sample command trace is provided in the traces/ folder. 4110428Sandreas.hansson@arm.com 4210428Sandreas.hansson@arm.com### Transaction Traces 4310428Sandreas.hansson@arm.comIf the transaction-level interface is being used, a transaction trace can be logged. 4410428Sandreas.hansson@arm.com 4510428Sandreas.hansson@arm.comThe format it uses is: ```<timestamp>,<transaction_type>,<address>```. 4610428Sandreas.hansson@arm.comFor example, "35,READ,0x80028", where READ/WRITE can be the transaction type and the logical address (32-bits long and byte addressable) less than the maximum supported DRAM capacity of 4GB (32Gb). 4710428Sandreas.hansson@arm.com 4810428Sandreas.hansson@arm.comThe tool uses a flexible and efficient memory map as follows: specified in HEX (0x). Timestamp is in clock cycles (cc) and maximum {row}-{bank}-{column}-{BI}-{BC}-{BGI}-{BL} 4910428Sandreas.hansson@arm.comHere, BI gives the degree of bank interleaving, BC gives the burst size (count), BGI gives the degree of bank group interleaving (for DDR4) and BL gives the burst length used by the device. 5010428Sandreas.hansson@arm.comDual-Rank addressing is not yet supported. The BC and BL address bits are derived from the column address bits, whereas the BI and BGI bits are derived from the bank address bits. 5110428Sandreas.hansson@arm.com 5210428Sandreas.hansson@arm.comFour sample MediaBench application transaction traces have been provided. The MediaBench applications include: (1) EPIC Encoder, (2) JPEG Encoder, (3) H263 Encoder and (4) MPEG2 Encoder. These applications were independently executed on the SimpleScalar simulator with a 16KB L1 D-cache, 16KB L1 I-cache, 128KB L2 cache and 64-byte cache line configuration. We filtered out the L2 cache misses meant for the DRAM and logged them as transaction traces. These can be used with our command scheduler to generate equivalent command traces for any DRAM memory specified. 5310428Sandreas.hansson@arm.com 5410428Sandreas.hansson@arm.com## 5. Usage 5510428Sandreas.hansson@arm.com 5612266Sradhika.jagtap@arm.com[drampower.cc](src/cli/drampower.cc) is the main interface file, which accepts user inputs to specify memory to be employed and the command or transaction trace to be analyzed. If the transaction trace (DRAM command scheduler) is being used, the users can specify the degree of bank interleaving required, the request size and the use of power-down or self-refresh options. Also, for DDR4 memories bank group interleaving can be specified. Dual-rank DRAMs are not yet supported by the command scheduler. Note: Speculative use of power-down or self-refresh modes will increase the trace length due to the power-up latencies of these power-saving modes. 5710428Sandreas.hansson@arm.com 5810428Sandreas.hansson@arm.comTo use DRAMPower at the command-level (command trace), after make, use the following: 5910428Sandreas.hansson@arm.com```bash 6010428Sandreas.hansson@arm.com./drampower -m <memory spec (ID)> -c <commands trace> 6110428Sandreas.hansson@arm.com``` 6210428Sandreas.hansson@arm.comTo use DRAMPower at the transaction-level (command scheduler), after make, use the 6310428Sandreas.hansson@arm.comfollowing: 6410428Sandreas.hansson@arm.com```bash 6510428Sandreas.hansson@arm.com./drampower -m <memory spec (ID)> -t <transactions trace> 6610428Sandreas.hansson@arm.com``` 6710428Sandreas.hansson@arm.comAdditional options when using transactions trace [-t] include: 6810428Sandreas.hansson@arm.com * [-i] ```<interleaving>``` 6910428Sandreas.hansson@arm.com * [-s] ```<request size>``` 7010428Sandreas.hansson@arm.com * [-g] ```<DDR4 bank group interleaving>``` 7110428Sandreas.hansson@arm.com * [-p] ```<0 - No Power-Down, 1 - Power-Down, 2 - Self-Refresh>``` 7210428Sandreas.hansson@arm.com 7310428Sandreas.hansson@arm.comAlso, when using either the commands trace or the transactions trace, the user can 7410428Sandreas.hansson@arm.comoptionally include IO and Termination power estimates (obtained from Micron's DRAM 7510428Sandreas.hansson@arm.comPower Calculator). To enable the same, the '-r' flag can be employed in command line. 7610428Sandreas.hansson@arm.com 7710428Sandreas.hansson@arm.comIf these options are not used, the default values assumed are: 7810428Sandreas.hansson@arm.com* interleaving = 1 7910428Sandreas.hansson@arm.com* request size = burst length * I/O width / 8 (in bytes) (from memory XMLs) 8010428Sandreas.hansson@arm.com* power saving = No power-down 8110428Sandreas.hansson@arm.com* bank group interleaving = 1 8210428Sandreas.hansson@arm.com* IO and termination = OFF (0) 8310428Sandreas.hansson@arm.com* Burst size (count) of 1 8410428Sandreas.hansson@arm.com 8510428Sandreas.hansson@arm.com## 6. Memory Specifications 8610428Sandreas.hansson@arm.com 8710428Sandreas.hansson@arm.com36 sample memory specifications are given in the XMLs targeting DDR2/DDR3/DDR4, LPDDR/LPDDR2/LPDDR3 and WIDE IO DRAM devices. The memory specifications are based on 1Gb DDR2, 1Gb & 2Gb DDR3, 2Gb LPDDR/LPDDR2 and 4Gb DDR4/LPDDR3 Micron datasheets and the 256Mb Wide IO SDR specifications are based on JEDEC timing specifications and circuit-level IDD measurements by TU Kaiserslautern, inplace of the as yet unavailable vendor datasheets. 4 of the memory specifications target dual-rank DDR3 DIMMs. 8810428Sandreas.hansson@arm.com 8910428Sandreas.hansson@arm.comNote: The timing specifications in the XMLs are in clock cycles (cc). The current specifications for Reading and Writing do not include the I/O consumption. They are computed and included seperately based on Micron Power Calculator. The IDD measures associated with different power supply sources of equal measure (VDD2, VDDCA and VDDQ) for LPDDR2, LPDDR3, DDR4 and WIDE IO memories have been added up together for simplicity, since it does not impact power computation accuracy. The current measures for dual-rank DIMMs reflect only the measures for the active rank. The default state of the idle rank is assumed to be the same as the complete memory state, for background power estimation. Accordingly, in all dual-rank memory specifications, IDD2P0 has been subtracted from the active currents and all background currents have been halved. They are also accounted for seperately by the power model. Stacking multiple Wide IO DRAM dies can also be captured by the nbrOfRanks parameter. 9010428Sandreas.hansson@arm.com 9110428Sandreas.hansson@arm.com## 7. Variation-aware Power And Energy Estimation 9210428Sandreas.hansson@arm.com 9310428Sandreas.hansson@arm.com15 of the included datasheets reflect the impact of process-variations on DRAM currents for a selection of DDR3 memories manufactured at 50nm process technology. These memories include: 9410428Sandreas.hansson@arm.com(1) MICRON_128MB_DDR3-1066_8bit - revision G 9510428Sandreas.hansson@arm.com(2) MICRON_128MB_DDR3-1066_16bit - revision G 9610428Sandreas.hansson@arm.com(3) MICRON_128MB_DDR3-1600_8bit - revision G 9710428Sandreas.hansson@arm.com(4) MICRON_256MB_DDR3-1066_8bit - revision D 9810428Sandreas.hansson@arm.com(5) MICRON_256MB_DDR3-1600_16bit - revision D 9910428Sandreas.hansson@arm.com 10010428Sandreas.hansson@arm.comThe original vendor-provided datasheet current specifications are given in XMLs 10110428Sandreas.hansson@arm.comwithout suffixes such as _mu, _2s and _3s. XMLs including suffixes indicate that the 10210428Sandreas.hansson@arm.comcurrent measures are either: (1) typical (mu), or (2) include +2 sigma variation (2s), 10310428Sandreas.hansson@arm.comor (3) include +3 sigma variation (3s). These measures are derived based on the 10410428Sandreas.hansson@arm.comMonte-Carlo analysis performed on our SPICE-based DRAM cross-section. 10510428Sandreas.hansson@arm.com 10610428Sandreas.hansson@arm.comTo include these XMLs in your simulations, simply use them as the target memory. 10710428Sandreas.hansson@arm.com 10810428Sandreas.hansson@arm.com## 8. Example Usage 10910428Sandreas.hansson@arm.com 11010428Sandreas.hansson@arm.comAn example of using this tool is provided below. To compile the example, 11112266Sradhika.jagtap@arm.comuse the Makefile and make sure the gcc and Xerces-c are installed. Then, run: 11210428Sandreas.hansson@arm.com``` 11310428Sandreas.hansson@arm.commake -j4 11410428Sandreas.hansson@arm.com``` 11510428Sandreas.hansson@arm.comAfter this, run with the command trace or the transaction trace, as described before: 11610428Sandreas.hansson@arm.com``` 11710428Sandreas.hansson@arm.com./drampower -m memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml -t traces/mediabench-epic.trace -r 11810428Sandreas.hansson@arm.com``` 11910428Sandreas.hansson@arm.comThe output should be something like this: 12010428Sandreas.hansson@arm.com 12110428Sandreas.hansson@arm.com``` 12210428Sandreas.hansson@arm.com* Parsing memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml 12312266Sradhika.jagtap@arm.com* Analysis start time: Thu Aug 4 15:43:52 2016 12410428Sandreas.hansson@arm.com* Analyzing the input trace 12510428Sandreas.hansson@arm.com* Trace Details: 12612266Sradhika.jagtap@arm.com 12712266Sradhika.jagtap@arm.com#ACT commands: 96984 12812266Sradhika.jagtap@arm.com#RD + #RDA commands: 67179 12912266Sradhika.jagtap@arm.com#WR + #WRA commands: 29805 13012266Sradhika.jagtap@arm.com#PRE (+ PREA) commands: 96984 13112266Sradhika.jagtap@arm.com#REF commands: 13168 13212266Sradhika.jagtap@arm.com#Active Cycles: 2519793 13312266Sradhika.jagtap@arm.com #Active Idle Cycles: 196851 13412266Sradhika.jagtap@arm.com #Active Power-Up Cycles: 0 13512266Sradhika.jagtap@arm.com #Auto-Refresh Active cycles during Self-Refresh Power-Up: 0 13612266Sradhika.jagtap@arm.com#Precharged Cycles: 52261474 13712266Sradhika.jagtap@arm.com #Precharged Idle Cycles: 51649629 13812266Sradhika.jagtap@arm.com #Precharged Power-Up Cycles: 0 13912266Sradhika.jagtap@arm.com #Auto-Refresh Precharged cycles during Self-Refresh Power-Up: 0 14012266Sradhika.jagtap@arm.com #Self-Refresh Power-Up Cycles: 0 14112266Sradhika.jagtap@arm.comTotal Idle Cycles (Active + Precharged): 51846480 14212266Sradhika.jagtap@arm.com#Power-Downs: 0 14312266Sradhika.jagtap@arm.com #Active Fast-exit Power-Downs: 0 14412266Sradhika.jagtap@arm.com #Active Slow-exit Power-Downs: 0 14512266Sradhika.jagtap@arm.com #Precharged Fast-exit Power-Downs: 0 14612266Sradhika.jagtap@arm.com #Precharged Slow-exit Power-Downs: 0 14712266Sradhika.jagtap@arm.com#Power-Down Cycles: 0 14812266Sradhika.jagtap@arm.com #Active Fast-exit Power-Down Cycles: 0 14912266Sradhika.jagtap@arm.com #Active Slow-exit Power-Down Cycles: 0 15012266Sradhika.jagtap@arm.com #Auto-Refresh Active cycles during Self-Refresh: 0 15112266Sradhika.jagtap@arm.com #Precharged Fast-exit Power-Down Cycles: 0 15212266Sradhika.jagtap@arm.com #Precharged Slow-exit Power-Down Cycles: 0 15312266Sradhika.jagtap@arm.com #Auto-Refresh Precharged cycles during Self-Refresh: 0 15412266Sradhika.jagtap@arm.com#Auto-Refresh Cycles: 776912 15512266Sradhika.jagtap@arm.com#Self-Refreshes: 0 15612266Sradhika.jagtap@arm.com#Self-Refresh Cycles: 0 15710428Sandreas.hansson@arm.com---------------------------------------- 15810428Sandreas.hansson@arm.comTotal Trace Length (clock cycles): 54781267 15910428Sandreas.hansson@arm.com---------------------------------------- 16010428Sandreas.hansson@arm.com 16110428Sandreas.hansson@arm.com* Trace Power and Energy Estimates: 16212266Sradhika.jagtap@arm.com 16310428Sandreas.hansson@arm.comACT Cmd Energy: 109175234.52 pJ 16410428Sandreas.hansson@arm.comPRE Cmd Energy: 47764165.10 pJ 16510428Sandreas.hansson@arm.comRD Cmd Energy: 49155365.85 pJ 16612266Sradhika.jagtap@arm.comWR Cmd Energy: 23486116.32 pJRD I/O Energy: 20872124.58 pJ 16712266Sradhika.jagtap@arm.comWR Termination Energy: 47419587.24 pJ 16810428Sandreas.hansson@arm.comACT Stdby Energy: 283653996.25 pJ 16910428Sandreas.hansson@arm.com Active Idle Energy: 22159587.24 pJ 17010428Sandreas.hansson@arm.com Active Power-Up Energy: 0.00 pJ 17110428Sandreas.hansson@arm.com Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ 17210428Sandreas.hansson@arm.comPRE Stdby Energy: 5147706163.23 pJ 17312266Sradhika.jagtap@arm.com Precharge Idle Energy: 5087440004.69 pJ 17410428Sandreas.hansson@arm.com Precharged Power-Up Energy: 0.00 pJ 17510428Sandreas.hansson@arm.com Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ 17610428Sandreas.hansson@arm.com Self-Refresh Power-Up Energy: 0.00 pJ 17712266Sradhika.jagtap@arm.comTotal Idle Energy (Active + Precharged): 5109599591.93 pJ 17810428Sandreas.hansson@arm.comTotal Power-Down Energy: 0.00 pJ 17910428Sandreas.hansson@arm.com Fast-Exit Active Power-Down Energy: 0.00 pJ 18010428Sandreas.hansson@arm.com Slow-Exit Active Power-Down Energy: 0.00 pJ 18110428Sandreas.hansson@arm.com Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ 18210428Sandreas.hansson@arm.com Fast-Exit Precharged Power-Down Energy: 0.00 pJ 18310428Sandreas.hansson@arm.com Slow-Exit Precharged Power-Down Energy: 0.00 pJ 18410428Sandreas.hansson@arm.com Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ 18510428Sandreas.hansson@arm.comAuto-Refresh Energy: 262371782.36 pJ 18610428Sandreas.hansson@arm.comSelf-Refresh Energy: 0.00 pJ 18710428Sandreas.hansson@arm.com---------------------------------------- 18812266Sradhika.jagtap@arm.comTotal Trace Energy: 5991604535.46 pJ 18912266Sradhika.jagtap@arm.comAverage Power: 58.30 mW 19010428Sandreas.hansson@arm.com---------------------------------------- 19112266Sradhika.jagtap@arm.com* Power Computation End time: Thu Aug 4 15:43:59 2016 19212266Sradhika.jagtap@arm.com* Total Simulation time: 7 seconds 19310428Sandreas.hansson@arm.com* 19410428Sandreas.hansson@arm.com``` 19510428Sandreas.hansson@arm.com 19610428Sandreas.hansson@arm.comAs can be noticed, the tool performs DRAM command scheduling and reports the number 19710428Sandreas.hansson@arm.comof activates, precharges, reads, writes, refreshes, power-downs and self-refreshes 19810428Sandreas.hansson@arm.combesides the number of clock cycles spent in the active and precharged states, in the 19910428Sandreas.hansson@arm.compower-down (fast/slow-exit) and self-refresh states and in the idle mode. It also 20010428Sandreas.hansson@arm.comreports the energy consumption of these components, besides the IO and Termination 20110428Sandreas.hansson@arm.comcomponents in pJ (pico Joules) and the average power consumption of the trace in mW. 20210428Sandreas.hansson@arm.comIt also reports the simulation start/end times and the total simulation time in seconds. 20310428Sandreas.hansson@arm.com 20410428Sandreas.hansson@arm.com## 9. DRAMPower Library 20510428Sandreas.hansson@arm.com 20610428Sandreas.hansson@arm.comThe DRAMPower tool has an additional feature and can be used as a library. 20712266Sradhika.jagtap@arm.comIn order to use the library run "make lib", include [LibDRAMPower.h](src/libdrampower/LibDRAMPower.h) in your project and 20810428Sandreas.hansson@arm.comlink the file src/libdrampower.a with your project. 20912266Sradhika.jagtap@arm.comExamples for the usage of the library are [lib_test.cc](test/libdrampowertest/lib_test.cc) and [window_example.cc](test/libdrampowertest/window_example.cc). 21010428Sandreas.hansson@arm.com 21110428Sandreas.hansson@arm.com## 10. Authors & Acknowledgment 21210428Sandreas.hansson@arm.com 21312266Sradhika.jagtap@arm.comThe tool is based on the DRAM power model developed jointly by the Computer Engineering Research Group at TU Delft and the Electronic Systems Group at TU Eindhoven 21412266Sradhika.jagtap@arm.comand verified by the Microelectronic System Design Research Group at TU Kaiserslautern with equivalent circuit-level simulations. This tool has been developed by 21512266Sradhika.jagtap@arm.comKarthik Chandrasekar with Yonghui Li under the supervision of Dr. Benny Akesson and Prof. Kees Goossens. The IO and Termination Power measures have been employed 21612266Sradhika.jagtap@arm.comfrom Micron's DRAM Power Calculator. If you decide to use DRAMPower in your research, please cite one of the following references: 21710428Sandreas.hansson@arm.com 21810428Sandreas.hansson@arm.com**To cite the DRAMPower Tool:** 21910428Sandreas.hansson@arm.com``` 22011555Sjungma@eit.uni-kl.de[1] DRAMPower: Open-source DRAM Power & Energy Estimation Tool 22111555Sjungma@eit.uni-kl.deKarthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens 22210428Sandreas.hansson@arm.comURL: http://www.drampower.info 22310428Sandreas.hansson@arm.com``` 22410428Sandreas.hansson@arm.com 22510428Sandreas.hansson@arm.com**To cite the DRAM power model:** 22610428Sandreas.hansson@arm.com``` 22710428Sandreas.hansson@arm.com[2] "Improved Power Modeling of DDR SDRAMs" 22810428Sandreas.hansson@arm.comKarthik Chandrasekar, Benny Akesson, and Kees Goossens 22910428Sandreas.hansson@arm.comIn Proc. 14th Euromicro Conference on Digital System Design (DSD), 2011 23010428Sandreas.hansson@arm.com``` 23110428Sandreas.hansson@arm.com 23210428Sandreas.hansson@arm.com**To cite the 3D-DRAM power model:** 23310428Sandreas.hansson@arm.com``` 23410428Sandreas.hansson@arm.com[3] "System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs" 23510428Sandreas.hansson@arm.comKarthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens 23610428Sandreas.hansson@arm.comIn Proc. Design, Automation and Test in Europe (DATE), 2013 23710428Sandreas.hansson@arm.com``` 23810428Sandreas.hansson@arm.com 23910428Sandreas.hansson@arm.com**To cite variation-aware DRAM power estimation:** 24010428Sandreas.hansson@arm.com``` 24110428Sandreas.hansson@arm.com[4] "Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach" 24210428Sandreas.hansson@arm.comKarthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens 24310428Sandreas.hansson@arm.comIn Proc. Design Automation Conference (DAC), 2013 24410428Sandreas.hansson@arm.com``` 24510428Sandreas.hansson@arm.com 24610428Sandreas.hansson@arm.com## 11. Contact Information 24710428Sandreas.hansson@arm.com 24810428Sandreas.hansson@arm.comFurther questions about the tool and the power model can be directed to: 24910428Sandreas.hansson@arm.com 25010428Sandreas.hansson@arm.comBenny Akesson (k.b.akesson@tue.nl) 25110428Sandreas.hansson@arm.com 25210428Sandreas.hansson@arm.comFeel free to ask for updates to the tool's features and please do report any bugs 25310428Sandreas.hansson@arm.comand errors you encounter. This will encourage us to continuously improve the tool. 25410428Sandreas.hansson@arm.com 25510428Sandreas.hansson@arm.com## Disclaimer 25610428Sandreas.hansson@arm.com 25710428Sandreas.hansson@arm.comThe tool does not check the timing accuracy of the user's memory command trace 25810428Sandreas.hansson@arm.comand the use of commands and memory modes. It is expected that the user employs 25910428Sandreas.hansson@arm.coma valid trace generated using a DRAM memory controller or simulator, which 26010428Sandreas.hansson@arm.comsatisfies all memory timing constraints and other requirements. The user DOES 26110428Sandreas.hansson@arm.comNOT get ANY WARRANTIES when using this tool. This software is released under the 26210428Sandreas.hansson@arm.comBSD 3-Clause License. By using this software, the user implicitly agrees to the 26310428Sandreas.hansson@arm.comlicensing terms. 264