ChangeLog revision 10428:0caf62b57dfd
110428Sandreas.hansson@arm.comChange Log: 210428Sandreas.hansson@arm.com 310428Sandreas.hansson@arm.comDRAMPower v4.0 - * DRAMPower can now be compiled as a library. This enables a user 410428Sandreas.hansson@arm.com to access the tool through an API and log commands and their 510428Sandreas.hansson@arm.com corresponding time stamps, removing the need to store large 610428Sandreas.hansson@arm.com command traces on disk. In addition, cycle counting variables 710428Sandreas.hansson@arm.com have been changed to int64 to support longer simulations. 810428Sandreas.hansson@arm.com The library can be compiled without Xerces to remove an optional 910428Sandreas.hansson@arm.com dependency and reduce the size of the binary. 1010428Sandreas.hansson@arm.com * Improved robustness. The latest build is automatically checked 1110428Sandreas.hansson@arm.com out on a test server, compiled, and tested to verify that the 1210428Sandreas.hansson@arm.com output matches an expected reference. The code is also compiled 1310428Sandreas.hansson@arm.com with a large number of warning flags enabled and treats all 1410428Sandreas.hansson@arm.com warnings as errors. 1510428Sandreas.hansson@arm.com * Bug fix: Fixed bug in io/termination energy calculation. 1610428Sandreas.hansson@arm.com * Bug fix: Fixed bug in calculation of auto precharge cycle. 1710428Sandreas.hansson@arm.com 1810428Sandreas.hansson@arm.comDRAMPower v3.1 - * Added IO and Termination Power measures from Micron's DRAM Power 1910428Sandreas.hansson@arm.com Calculator, for all supported DRAM generations. In the case of 2010428Sandreas.hansson@arm.com Wide IO DRAMs, these measures are already included in the provided 2110428Sandreas.hansson@arm.com current specifications. This feature enables support for multi-rank 2210428Sandreas.hansson@arm.com DRAM DIMMs (DDR2/3/4) and stacking of multiple Wide IO DRAM dies 2310428Sandreas.hansson@arm.com (equivalent to ranks). To indicate use of multi-rank DRAMs or 2410428Sandreas.hansson@arm.com multiple Wide IO DRAM dies/layers, the 'nbrOfRanks' parameter in 2510428Sandreas.hansson@arm.com the memory specification XMLs can be employed. Note: The DRAM 2610428Sandreas.hansson@arm.com command scheduler does not support multi-rank/multi-die DRAMs yet. 2710428Sandreas.hansson@arm.com Only the power estimation component of DRAMPower has been updated 2810428Sandreas.hansson@arm.com to support them. The current measures for dual-rank DRAMs only 2910428Sandreas.hansson@arm.com reflect those for the active rank and not the idle rank. The 3010428Sandreas.hansson@arm.com default state of the idle rank is assumed to be the same as the 3110428Sandreas.hansson@arm.com current memory state, for background power estimation. Hence, 3210428Sandreas.hansson@arm.com rank information in the command trace is not required. 3310428Sandreas.hansson@arm.com * Added warning messages: New warning messages are provided, to 3410428Sandreas.hansson@arm.com identify if the memory or bank state is inconsistent in the 3510428Sandreas.hansson@arm.com user-defined traces. Towards this, a state check is performed on 3610428Sandreas.hansson@arm.com every memory command issued. 3710428Sandreas.hansson@arm.com * Improved run-time options: Users can now point directly to the 3810428Sandreas.hansson@arm.com memory specification XML, instead of just the memory ID. Also, 3910428Sandreas.hansson@arm.com users can optionally include IO and termination power estimates 4010428Sandreas.hansson@arm.com (for both single and dual rank DRAMs) using '-r' flag in the 4110428Sandreas.hansson@arm.com command line options. 4210428Sandreas.hansson@arm.com * Bug fixes: (1) Refresh handler in the DRAM Command Scheduler was 4310428Sandreas.hansson@arm.com kept ON in the Self-Refresh mode, when it can be turned OFF. This 4410428Sandreas.hansson@arm.com bug has now been fixed. (2) Precharge All (PREA) always considered 4510428Sandreas.hansson@arm.com precharging of all banks. It has now been modified to consider 4610428Sandreas.hansson@arm.com precharging of the open/active banks alone. 4710428Sandreas.hansson@arm.com 4810428Sandreas.hansson@arm.comDRAMPower v3.0 - * Added support for LPDDR3 and DDR4 memories, besides the already 4910428Sandreas.hansson@arm.com supported DDR2/DDR3, LPDDR/LPDDR2 and WIDE IO DRAM memories. 5010428Sandreas.hansson@arm.com * Added DRAM Command Scheduler: To support users of DRAMPower 5110428Sandreas.hansson@arm.com without access to DRAM controllers, we have added a simple DRAM 5210428Sandreas.hansson@arm.com command scheduler that dynamically schedules DRAM commands as if 5310428Sandreas.hansson@arm.com it were a memory controller. The scheduler assumes closed-page 5410428Sandreas.hansson@arm.com policy, employs ASAP scheduling for DRAM commands (i.e. schedules 5510428Sandreas.hansson@arm.com commands as soon as timing constraints are met), performs FCFS 5610428Sandreas.hansson@arm.com scheduling on DRAM transactions and supports all the different 5710428Sandreas.hansson@arm.com DRAM generations supported by the power model. The generated DRAM 5810428Sandreas.hansson@arm.com command schedule is also analyzable for real-time applications. 5910428Sandreas.hansson@arm.com Users can also select speculative usage of power-down or 6010428Sandreas.hansson@arm.com self-refresh modes (if needed) for idle periods between 6112266Sradhika.jagtap@arm.com transactions. It should be noted that using this command scheduler 6210428Sandreas.hansson@arm.com is optional and it can be (de-)selected during run-time and users 6310428Sandreas.hansson@arm.com can switch back to the previously used DRAM command interface as 6410428Sandreas.hansson@arm.com in the earlier versions. 6510428Sandreas.hansson@arm.com * Improved run-time options: Users can specify the memory and the 6610428Sandreas.hansson@arm.com trace file to be used by DRAMPower using command line options. 6710428Sandreas.hansson@arm.com Additionally, if the DRAM command scheduler is being used, the 6810428Sandreas.hansson@arm.com users can specify the degree of bank interleaving required, the 6910428Sandreas.hansson@arm.com request size and power-down or self-refresh options. Also, for 7010428Sandreas.hansson@arm.com DDR4 memories the bank group interleaving can be specified using 7110428Sandreas.hansson@arm.com command line options. 7210428Sandreas.hansson@arm.com * Bug fixes: (1) For command traces ending with a RD/WR/RDA/WRA 7310428Sandreas.hansson@arm.com command, the tool did not consider completion of operations when 7410428Sandreas.hansson@arm.com estimating the total trace energy. The missing cycles are now 7510428Sandreas.hansson@arm.com taken into account. 7610428Sandreas.hansson@arm.com (2) The IDD5 (REF current) specification for WIDE IO SDR memory 7710428Sandreas.hansson@arm.com specifications only included 2 banks for refreshes instead of all 7810428Sandreas.hansson@arm.com four. We would like to thank David Roberts from AMD for spotting 7910428Sandreas.hansson@arm.com the issue in our DATE'13 article. These measures have been updated. 8010428Sandreas.hansson@arm.com (3) When estimating precharge cycle for commands with 8110428Sandreas.hansson@arm.com auto-precharge, (RDA/WRA), the command analysis tool employed the 8210428Sandreas.hansson@arm.com last activation cycle in the entire DRAM instead of the particular 8310428Sandreas.hansson@arm.com DRAM bank. This bug has been fixed in this release. 8410428Sandreas.hansson@arm.com 8510428Sandreas.hansson@arm.comDRAMPower v2.1 - * Added support for variation-aware power estimation, for a 8610428Sandreas.hansson@arm.com selection of DDR3 memories manufactured using 50nm process 8710428Sandreas.hansson@arm.com technology, based on the Monte-Carlo analysis presented in our 8810428Sandreas.hansson@arm.com DAC'13 article. 8910428Sandreas.hansson@arm.com 9010428Sandreas.hansson@arm.comDRAMPower v2.0 - * Added support for LPDDR/LPDDR2 and WIDE IO DRAM memories, besides 9110428Sandreas.hansson@arm.com the already supported DDR2/DDR3 memories. 9210428Sandreas.hansson@arm.com * Faster analysis: The trace analysis component in DRAMPower v2.0 9310428Sandreas.hansson@arm.com triggers the evaluation only during memory state transitions 9410428Sandreas.hansson@arm.com (between active, precharged, active and precharged power-down, 9510428Sandreas.hansson@arm.com refresh, self-refresh and power-up states) and not on every clock 9610428Sandreas.hansson@arm.com cycle, as was the case till the last version. This optimization 9710428Sandreas.hansson@arm.com speeds up the power simulations using DRAMPower by several times 9812266Sradhika.jagtap@arm.com over cycle-accurate analysis, resulting in fast power analysis, 9910428Sandreas.hansson@arm.com without affecting the accuracy of the trace analysis or the 10010428Sandreas.hansson@arm.com reported power and energy estimates. 10110428Sandreas.hansson@arm.com * Verification effort: Our power model was verified by the 10210428Sandreas.hansson@arm.com Microelectronic System Design group at TU Kaiserslautern using 10310428Sandreas.hansson@arm.com circuit-level SPICE simulations of a DRAM cross-section. As a 10410428Sandreas.hansson@arm.com result of this verification effort, a couple of power equations 10510428Sandreas.hansson@arm.com have been modified for Refresh and Self-refresh operations. The 10610428Sandreas.hansson@arm.com difference between the power and energy estimates reported by our 10710428Sandreas.hansson@arm.com updated model and the equivalent circuit-level simulations is 10810428Sandreas.hansson@arm.com < 2% for all memory operations of any granularity for all memories 10910428Sandreas.hansson@arm.com supported by DRAMPower. 11010428Sandreas.hansson@arm.com 11110428Sandreas.hansson@arm.comDRAMPower v1.2 - * Supports different power-down and self-refresh modes in DDR2 and 11210428Sandreas.hansson@arm.com DDR3 DRAM memories. 113 * Bug fix: Refresh power consumption equation in DRAMPower v1, 114 incorrectly subtracted IDD2n (precharge background current) 115 instead of IDD3n (active background current) from IDD5 (total 116 refresh current). This error has been rectified in this version. 117 118DRAMPower v1.0 - * Performs cycle-accurate memory command trace analysis and estimates 119 power and energy consumption numbers for the trace. 120 * It supports the basic memory operations like read, write, refresh, 121 activate and (auto) precharge in DDR2 and DDR3 memories. 122