ChangeLog revision 10428:0caf62b57dfd
1Change Log: 2 3DRAMPower v4.0 - * DRAMPower can now be compiled as a library. This enables a user 4 to access the tool through an API and log commands and their 5 corresponding time stamps, removing the need to store large 6 command traces on disk. In addition, cycle counting variables 7 have been changed to int64 to support longer simulations. 8 The library can be compiled without Xerces to remove an optional 9 dependency and reduce the size of the binary. 10 * Improved robustness. The latest build is automatically checked 11 out on a test server, compiled, and tested to verify that the 12 output matches an expected reference. The code is also compiled 13 with a large number of warning flags enabled and treats all 14 warnings as errors. 15 * Bug fix: Fixed bug in io/termination energy calculation. 16 * Bug fix: Fixed bug in calculation of auto precharge cycle. 17 18DRAMPower v3.1 - * Added IO and Termination Power measures from Micron's DRAM Power 19 Calculator, for all supported DRAM generations. In the case of 20 Wide IO DRAMs, these measures are already included in the provided 21 current specifications. This feature enables support for multi-rank 22 DRAM DIMMs (DDR2/3/4) and stacking of multiple Wide IO DRAM dies 23 (equivalent to ranks). To indicate use of multi-rank DRAMs or 24 multiple Wide IO DRAM dies/layers, the 'nbrOfRanks' parameter in 25 the memory specification XMLs can be employed. Note: The DRAM 26 command scheduler does not support multi-rank/multi-die DRAMs yet. 27 Only the power estimation component of DRAMPower has been updated 28 to support them. The current measures for dual-rank DRAMs only 29 reflect those for the active rank and not the idle rank. The 30 default state of the idle rank is assumed to be the same as the 31 current memory state, for background power estimation. Hence, 32 rank information in the command trace is not required. 33 * Added warning messages: New warning messages are provided, to 34 identify if the memory or bank state is inconsistent in the 35 user-defined traces. Towards this, a state check is performed on 36 every memory command issued. 37 * Improved run-time options: Users can now point directly to the 38 memory specification XML, instead of just the memory ID. Also, 39 users can optionally include IO and termination power estimates 40 (for both single and dual rank DRAMs) using '-r' flag in the 41 command line options. 42 * Bug fixes: (1) Refresh handler in the DRAM Command Scheduler was 43 kept ON in the Self-Refresh mode, when it can be turned OFF. This 44 bug has now been fixed. (2) Precharge All (PREA) always considered 45 precharging of all banks. It has now been modified to consider 46 precharging of the open/active banks alone. 47 48DRAMPower v3.0 - * Added support for LPDDR3 and DDR4 memories, besides the already 49 supported DDR2/DDR3, LPDDR/LPDDR2 and WIDE IO DRAM memories. 50 * Added DRAM Command Scheduler: To support users of DRAMPower 51 without access to DRAM controllers, we have added a simple DRAM 52 command scheduler that dynamically schedules DRAM commands as if 53 it were a memory controller. The scheduler assumes closed-page 54 policy, employs ASAP scheduling for DRAM commands (i.e. schedules 55 commands as soon as timing constraints are met), performs FCFS 56 scheduling on DRAM transactions and supports all the different 57 DRAM generations supported by the power model. The generated DRAM 58 command schedule is also analyzable for real-time applications. 59 Users can also select speculative usage of power-down or 60 self-refresh modes (if needed) for idle periods between 61 transactions. It should be noted that using this command scheduler 62 is optional and it can be (de-)selected during run-time and users 63 can switch back to the previously used DRAM command interface as 64 in the earlier versions. 65 * Improved run-time options: Users can specify the memory and the 66 trace file to be used by DRAMPower using command line options. 67 Additionally, if the DRAM command scheduler is being used, the 68 users can specify the degree of bank interleaving required, the 69 request size and power-down or self-refresh options. Also, for 70 DDR4 memories the bank group interleaving can be specified using 71 command line options. 72 * Bug fixes: (1) For command traces ending with a RD/WR/RDA/WRA 73 command, the tool did not consider completion of operations when 74 estimating the total trace energy. The missing cycles are now 75 taken into account. 76 (2) The IDD5 (REF current) specification for WIDE IO SDR memory 77 specifications only included 2 banks for refreshes instead of all 78 four. We would like to thank David Roberts from AMD for spotting 79 the issue in our DATE'13 article. These measures have been updated. 80 (3) When estimating precharge cycle for commands with 81 auto-precharge, (RDA/WRA), the command analysis tool employed the 82 last activation cycle in the entire DRAM instead of the particular 83 DRAM bank. This bug has been fixed in this release. 84 85DRAMPower v2.1 - * Added support for variation-aware power estimation, for a 86 selection of DDR3 memories manufactured using 50nm process 87 technology, based on the Monte-Carlo analysis presented in our 88 DAC'13 article. 89 90DRAMPower v2.0 - * Added support for LPDDR/LPDDR2 and WIDE IO DRAM memories, besides 91 the already supported DDR2/DDR3 memories. 92 * Faster analysis: The trace analysis component in DRAMPower v2.0 93 triggers the evaluation only during memory state transitions 94 (between active, precharged, active and precharged power-down, 95 refresh, self-refresh and power-up states) and not on every clock 96 cycle, as was the case till the last version. This optimization 97 speeds up the power simulations using DRAMPower by several times 98 over cycle-accurate analysis, resulting in fast power analysis, 99 without affecting the accuracy of the trace analysis or the 100 reported power and energy estimates. 101 * Verification effort: Our power model was verified by the 102 Microelectronic System Design group at TU Kaiserslautern using 103 circuit-level SPICE simulations of a DRAM cross-section. As a 104 result of this verification effort, a couple of power equations 105 have been modified for Refresh and Self-refresh operations. The 106 difference between the power and energy estimates reported by our 107 updated model and the equivalent circuit-level simulations is 108 < 2% for all memory operations of any granularity for all memories 109 supported by DRAMPower. 110 111DRAMPower v1.2 - * Supports different power-down and self-refresh modes in DDR2 and 112 DDR3 DRAM memories. 113 * Bug fix: Refresh power consumption equation in DRAMPower v1, 114 incorrectly subtracted IDD2n (precharge background current) 115 instead of IDD3n (active background current) from IDD5 (total 116 refresh current). This error has been rectified in this version. 117 118DRAMPower v1.0 - * Performs cycle-accurate memory command trace analysis and estimates 119 power and energy consumption numbers for the trace. 120 * It supports the basic memory operations like read, write, refresh, 121 activate and (auto) precharge in DDR2 and DDR3 memories. 122