MeshDirCorners_XY.py revision 11666
15390SN/A# Copyright (c) 2010 Advanced Micro Devices, Inc. 25390SN/A# All rights reserved. 35390SN/A# 45390SN/A# Redistribution and use in source and binary forms, with or without 55390SN/A# modification, are permitted provided that the following conditions are 65390SN/A# met: redistributions of source code must retain the above copyright 75390SN/A# notice, this list of conditions and the following disclaimer; 85390SN/A# redistributions in binary form must reproduce the above copyright 95390SN/A# notice, this list of conditions and the following disclaimer in the 105390SN/A# documentation and/or other materials provided with the distribution; 115390SN/A# neither the name of the copyright holders nor the names of its 125390SN/A# contributors may be used to endorse or promote products derived from 135390SN/A# this software without specific prior written permission. 145390SN/A# 155390SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165390SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175390SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185390SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195390SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205390SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215390SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225390SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235390SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245390SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255390SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265390SN/A# 275390SN/A# Authors: Brad Beckmann 285390SN/A 295390SN/Afrom m5.params import * 305390SN/Afrom m5.objects import * 315631Sgblack@eecs.umich.edu 328232Snate@binkert.orgfrom BaseTopology import SimpleTopology 335657Sgblack@eecs.umich.edu 345630Sgblack@eecs.umich.edu# Creates a Mesh topology with 4 directories, one at each corner. 355698Snate@binkert.org# One L1 (and L2, depending on the protocol) are connected to each router. 365698Snate@binkert.org# XY routing is enforced (using link weights) to guarantee deadlock freedom. 375390SN/A 389808Sstever@gmail.comclass MeshDirCorners_XY(SimpleTopology): 399808Sstever@gmail.com description='MeshDirCorners_XY' 409808Sstever@gmail.com 419808Sstever@gmail.com def __init__(self, controllers): 429808Sstever@gmail.com self.nodes = controllers 439808Sstever@gmail.com 445657Sgblack@eecs.umich.edu def makeTopology(self, options, network, IntLink, ExtLink, Router): 455827Sgblack@eecs.umich.edu nodes = self.nodes 465827Sgblack@eecs.umich.edu 475657Sgblack@eecs.umich.edu num_routers = options.num_cpus 485657Sgblack@eecs.umich.edu num_rows = options.mesh_rows 495390SN/A 505390SN/A # default values for link latency and router latency. 515390SN/A # Can be over-ridden on a per link/router basis 525631Sgblack@eecs.umich.edu link_latency = options.link_latency # used by simple and garnet 535631Sgblack@eecs.umich.edu router_latency = options.router_latency # only used by garnet 545631Sgblack@eecs.umich.edu 555631Sgblack@eecs.umich.edu 565631Sgblack@eecs.umich.edu # First determine which nodes are cache cntrls vs. dirs vs. dma 575631Sgblack@eecs.umich.edu cache_nodes = [] 585631Sgblack@eecs.umich.edu dir_nodes = [] 595631Sgblack@eecs.umich.edu dma_nodes = [] 605631Sgblack@eecs.umich.edu for node in nodes: 615631Sgblack@eecs.umich.edu if node.type == 'L1Cache_Controller' or \ 625631Sgblack@eecs.umich.edu node.type == 'L2Cache_Controller': 635631Sgblack@eecs.umich.edu cache_nodes.append(node) 645631Sgblack@eecs.umich.edu elif node.type == 'Directory_Controller': 655631Sgblack@eecs.umich.edu dir_nodes.append(node) 665631Sgblack@eecs.umich.edu elif node.type == 'DMA_Controller': 675631Sgblack@eecs.umich.edu dma_nodes.append(node) 685631Sgblack@eecs.umich.edu 695898Sgblack@eecs.umich.edu # Obviously the number or rows must be <= the number of routers 705630Sgblack@eecs.umich.edu # and evenly divisible. Also the number of caches must be a 715390SN/A # multiple of the number of routers and the number of directories 725390SN/A # must be four. 735390SN/A assert(num_rows > 0 and num_rows <= num_routers) 745390SN/A num_columns = int(num_routers / num_rows) 755390SN/A assert(num_columns * num_rows == num_routers) 765631Sgblack@eecs.umich.edu caches_per_router, remainder = divmod(len(cache_nodes), num_routers) 775631Sgblack@eecs.umich.edu assert(remainder == 0) 785631Sgblack@eecs.umich.edu assert(len(dir_nodes) == 4) 795631Sgblack@eecs.umich.edu 805631Sgblack@eecs.umich.edu # Create the routers in the mesh 815631Sgblack@eecs.umich.edu routers = [Router(router_id=i, latency = router_latency) \ 825631Sgblack@eecs.umich.edu for i in range(num_routers)] 835631Sgblack@eecs.umich.edu network.routers = routers 845631Sgblack@eecs.umich.edu 855631Sgblack@eecs.umich.edu # link counter to set unique link ids 865631Sgblack@eecs.umich.edu link_count = 0 875631Sgblack@eecs.umich.edu 885631Sgblack@eecs.umich.edu # Connect each cache controller to the appropriate router 895631Sgblack@eecs.umich.edu ext_links = [] 905688Sgblack@eecs.umich.edu for (i, n) in enumerate(cache_nodes): 915688Sgblack@eecs.umich.edu cntrl_level, router_id = divmod(i, num_routers) 925688Sgblack@eecs.umich.edu assert(cntrl_level < caches_per_router) 935631Sgblack@eecs.umich.edu ext_links.append(ExtLink(link_id=link_count, ext_node=n, 945631Sgblack@eecs.umich.edu int_node=routers[router_id], 955631Sgblack@eecs.umich.edu latency = link_latency)) 965631Sgblack@eecs.umich.edu link_count += 1 975631Sgblack@eecs.umich.edu 985631Sgblack@eecs.umich.edu # Connect the dir nodes to the corners. 995631Sgblack@eecs.umich.edu ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0], 1005631Sgblack@eecs.umich.edu int_node=routers[0], 1015631Sgblack@eecs.umich.edu latency = link_latency)) 1025631Sgblack@eecs.umich.edu link_count += 1 1035687Sgblack@eecs.umich.edu ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1], 1045687Sgblack@eecs.umich.edu int_node=routers[num_columns - 1], 1055687Sgblack@eecs.umich.edu latency = link_latency)) 1065687Sgblack@eecs.umich.edu link_count += 1 1075687Sgblack@eecs.umich.edu ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2], 1085687Sgblack@eecs.umich.edu int_node=routers[num_routers - num_columns], 1095631Sgblack@eecs.umich.edu latency = link_latency)) 1105631Sgblack@eecs.umich.edu link_count += 1 1115631Sgblack@eecs.umich.edu ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3], 1125631Sgblack@eecs.umich.edu int_node=routers[num_routers - 1], 1135631Sgblack@eecs.umich.edu latency = link_latency)) 1145686Sgblack@eecs.umich.edu link_count += 1 1155686Sgblack@eecs.umich.edu 1165686Sgblack@eecs.umich.edu # Connect the dma nodes to router 0. These should only be DMA nodes. 1175686Sgblack@eecs.umich.edu for (i, node) in enumerate(dma_nodes): 1185686Sgblack@eecs.umich.edu assert(node.type == 'DMA_Controller') 1195686Sgblack@eecs.umich.edu ext_links.append(ExtLink(link_id=link_count, ext_node=node, 1205631Sgblack@eecs.umich.edu int_node=routers[0], 1215631Sgblack@eecs.umich.edu latency = link_latency)) 1225631Sgblack@eecs.umich.edu 1235631Sgblack@eecs.umich.edu network.ext_links = ext_links 1245631Sgblack@eecs.umich.edu 1255631Sgblack@eecs.umich.edu # Create the mesh links. 1265631Sgblack@eecs.umich.edu int_links = [] 1275631Sgblack@eecs.umich.edu 1285631Sgblack@eecs.umich.edu # East output to West input links (weight = 1) 1295631Sgblack@eecs.umich.edu for row in xrange(num_rows): 1305631Sgblack@eecs.umich.edu for col in xrange(num_columns): 1315631Sgblack@eecs.umich.edu if (col + 1 < num_columns): 1325631Sgblack@eecs.umich.edu east_out = col + (row * num_columns) 1335631Sgblack@eecs.umich.edu west_in = (col + 1) + (row * num_columns) 1345631Sgblack@eecs.umich.edu int_links.append(IntLink(link_id=link_count, 1355631Sgblack@eecs.umich.edu src_node=routers[east_out], 1365631Sgblack@eecs.umich.edu dst_node=routers[west_in], 1375631Sgblack@eecs.umich.edu src_outport="East", 1385631Sgblack@eecs.umich.edu dst_inport="West", 1395631Sgblack@eecs.umich.edu latency = link_latency, 1405631Sgblack@eecs.umich.edu weight=1)) 1415631Sgblack@eecs.umich.edu link_count += 1 1425631Sgblack@eecs.umich.edu 1435631Sgblack@eecs.umich.edu # West output to East input links (weight = 1) 1445631Sgblack@eecs.umich.edu for row in xrange(num_rows): 1455631Sgblack@eecs.umich.edu for col in xrange(num_columns): 1465631Sgblack@eecs.umich.edu if (col + 1 < num_columns): 1475631Sgblack@eecs.umich.edu east_in = col + (row * num_columns) 1485631Sgblack@eecs.umich.edu west_out = (col + 1) + (row * num_columns) 1495631Sgblack@eecs.umich.edu int_links.append(IntLink(link_id=link_count, 1505631Sgblack@eecs.umich.edu src_node=routers[west_out], 1515631Sgblack@eecs.umich.edu dst_node=routers[east_in], 1525631Sgblack@eecs.umich.edu src_outport="West", 1535631Sgblack@eecs.umich.edu dst_inport="East", 1545631Sgblack@eecs.umich.edu latency = link_latency, 1555631Sgblack@eecs.umich.edu weight=1)) 1565631Sgblack@eecs.umich.edu link_count += 1 1575631Sgblack@eecs.umich.edu 1585631Sgblack@eecs.umich.edu # North output to South input links (weight = 2) 1595656Sgblack@eecs.umich.edu for col in xrange(num_columns): 1605631Sgblack@eecs.umich.edu for row in xrange(num_rows): 1615656Sgblack@eecs.umich.edu if (row + 1 < num_rows): 1625631Sgblack@eecs.umich.edu north_out = col + (row * num_columns) 1635631Sgblack@eecs.umich.edu south_in = col + ((row + 1) * num_columns) 1645631Sgblack@eecs.umich.edu int_links.append(IntLink(link_id=link_count, 1655632Sgblack@eecs.umich.edu src_node=routers[north_out], 1665631Sgblack@eecs.umich.edu dst_node=routers[south_in], 1675631Sgblack@eecs.umich.edu src_outport="North", 1685631Sgblack@eecs.umich.edu dst_inport="South", 1695631Sgblack@eecs.umich.edu latency = link_latency, 1705631Sgblack@eecs.umich.edu weight=2)) 1715634Sgblack@eecs.umich.edu link_count += 1 1725631Sgblack@eecs.umich.edu 1735631Sgblack@eecs.umich.edu # South output to North input links (weight = 2) 1745631Sgblack@eecs.umich.edu for col in xrange(num_columns): 1755631Sgblack@eecs.umich.edu for row in xrange(num_rows): 1765631Sgblack@eecs.umich.edu if (row + 1 < num_rows): 1775631Sgblack@eecs.umich.edu north_in = col + (row * num_columns) 1785631Sgblack@eecs.umich.edu south_out = col + ((row + 1) * num_columns) 1795631Sgblack@eecs.umich.edu int_links.append(IntLink(link_id=link_count, 1805631Sgblack@eecs.umich.edu src_node=routers[south_out], 1815632Sgblack@eecs.umich.edu dst_node=routers[north_in], 1825631Sgblack@eecs.umich.edu src_outport="South", 1835631Sgblack@eecs.umich.edu dst_inport="North", 1845632Sgblack@eecs.umich.edu latency = link_latency, 1855631Sgblack@eecs.umich.edu weight=2)) 1865631Sgblack@eecs.umich.edu link_count += 1 1875631Sgblack@eecs.umich.edu 1885631Sgblack@eecs.umich.edu 1895631Sgblack@eecs.umich.edu network.int_links = int_links 1905631Sgblack@eecs.umich.edu