run.py revision 7525
14403Srdreslin@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 21693Sstever@eecs.umich.edu# All rights reserved. 31693Sstever@eecs.umich.edu# 41693Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 51693Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 61693Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 71693Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 81693Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 91693Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 101693Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 111693Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 121693Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 131693Sstever@eecs.umich.edu# this software without specific prior written permission. 141693Sstever@eecs.umich.edu# 151693Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 161693Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 171693Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 181693Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 191693Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 201693Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 211693Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 221693Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 231693Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 241693Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 251693Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 261693Sstever@eecs.umich.edu# 271693Sstever@eecs.umich.edu# Authors: Ron Dreslinski 281693Sstever@eecs.umich.edu 293358Srdreslin@umich.edu# Splash2 Run Script 303358Srdreslin@umich.edu# 311516SN/A 326654Snate@binkert.orgimport os 336654Snate@binkert.orgimport optparse 346654Snate@binkert.orgimport sys 356654Snate@binkert.org 363358Srdreslin@umich.eduimport m5 373358Srdreslin@umich.edufrom m5.objects import * 386654Snate@binkert.org 396654Snate@binkert.orgm5.util.addToPath('../common') 401516SN/A 413358Srdreslin@umich.edu# -------------------- 423358Srdreslin@umich.edu# Define Command Line Options 433358Srdreslin@umich.edu# ==================== 443358Srdreslin@umich.edu 453358Srdreslin@umich.eduparser = optparse.OptionParser() 463358Srdreslin@umich.edu 473358Srdreslin@umich.eduparser.add_option("-d", "--detailed", action="store_true") 483358Srdreslin@umich.eduparser.add_option("-t", "--timing", action="store_true") 493358Srdreslin@umich.eduparser.add_option("-m", "--maxtick", type="int") 503358Srdreslin@umich.eduparser.add_option("-n", "--numcpus", 513358Srdreslin@umich.edu help="Number of cpus in total", type="int") 523358Srdreslin@umich.eduparser.add_option("-f", "--frequency", 533360Srdreslin@umich.edu default = "1GHz", 543358Srdreslin@umich.edu help="Frequency of each CPU") 553360Srdreslin@umich.eduparser.add_option("--l1size", 563360Srdreslin@umich.edu default = "32kB") 573360Srdreslin@umich.eduparser.add_option("--l1latency", 585255Ssaidi@eecs.umich.edu default = "1ns") 593360Srdreslin@umich.eduparser.add_option("--l2size", 603360Srdreslin@umich.edu default = "256kB") 613360Srdreslin@umich.eduparser.add_option("--l2latency", 625255Ssaidi@eecs.umich.edu default = "10ns") 633358Srdreslin@umich.eduparser.add_option("--rootdir", 644403Srdreslin@umich.edu help="Root directory of Splash2", 653360Srdreslin@umich.edu default="/dist/splash2/codes") 663358Srdreslin@umich.eduparser.add_option("-b", "--benchmark", 673358Srdreslin@umich.edu help="Splash 2 benchmark to run") 683358Srdreslin@umich.edu 693358Srdreslin@umich.edu(options, args) = parser.parse_args() 703358Srdreslin@umich.edu 713358Srdreslin@umich.eduif args: 723358Srdreslin@umich.edu print "Error: script doesn't take any positional arguments" 733358Srdreslin@umich.edu sys.exit(1) 743358Srdreslin@umich.edu 753360Srdreslin@umich.eduif not options.numcpus: 763360Srdreslin@umich.edu print "Specify the number of cpus with -n" 773360Srdreslin@umich.edu sys.exit(1) 783360Srdreslin@umich.edu 793358Srdreslin@umich.edu# -------------------- 803358Srdreslin@umich.edu# Define Splash2 Benchmarks 813358Srdreslin@umich.edu# ==================== 823358Srdreslin@umich.educlass Cholesky(LiveProcess): 834403Srdreslin@umich.edu cwd = options.rootdir + '/kernels/cholesky' 844403Srdreslin@umich.edu executable = options.rootdir + '/kernels/cholesky/CHOLESKY' 855256Ssaidi@eecs.umich.edu cmd = ['CHOLESKY', '-p' + str(options.numcpus), 865255Ssaidi@eecs.umich.edu options.rootdir + '/kernels/cholesky/inputs/tk23.O'] 873358Srdreslin@umich.edu 883358Srdreslin@umich.educlass FFT(LiveProcess): 894403Srdreslin@umich.edu cwd = options.rootdir + '/kernels/fft' 904403Srdreslin@umich.edu executable = options.rootdir + '/kernels/fft/FFT' 915255Ssaidi@eecs.umich.edu cmd = ['FFT', '-p', str(options.numcpus), '-m18'] 923358Srdreslin@umich.edu 933358Srdreslin@umich.educlass LU_contig(LiveProcess): 944403Srdreslin@umich.edu executable = options.rootdir + '/kernels/lu/contiguous_blocks/LU' 955255Ssaidi@eecs.umich.edu cmd = ['LU', '-p', str(options.numcpus)] 964403Srdreslin@umich.edu cwd = options.rootdir + '/kernels/lu/contiguous_blocks' 973358Srdreslin@umich.edu 983358Srdreslin@umich.educlass LU_noncontig(LiveProcess): 994403Srdreslin@umich.edu executable = options.rootdir + '/kernels/lu/non_contiguous_blocks/LU' 1005255Ssaidi@eecs.umich.edu cmd = ['LU', '-p', str(options.numcpus)] 1014403Srdreslin@umich.edu cwd = options.rootdir + '/kernels/lu/non_contiguous_blocks' 1023358Srdreslin@umich.edu 1033358Srdreslin@umich.educlass Radix(LiveProcess): 1044403Srdreslin@umich.edu executable = options.rootdir + '/kernels/radix/RADIX' 1055255Ssaidi@eecs.umich.edu cmd = ['RADIX', '-n524288', '-p', str(options.numcpus)] 1064403Srdreslin@umich.edu cwd = options.rootdir + '/kernels/radix' 1073358Srdreslin@umich.edu 1083358Srdreslin@umich.educlass Barnes(LiveProcess): 1094403Srdreslin@umich.edu executable = options.rootdir + '/apps/barnes/BARNES' 1105255Ssaidi@eecs.umich.edu cmd = ['BARNES'] 1114403Srdreslin@umich.edu input = options.rootdir + '/apps/barnes/input.p' + str(options.numcpus) 1124403Srdreslin@umich.edu cwd = options.rootdir + '/apps/barnes' 1133358Srdreslin@umich.edu 1143358Srdreslin@umich.educlass FMM(LiveProcess): 1154403Srdreslin@umich.edu executable = options.rootdir + '/apps/fmm/FMM' 1165255Ssaidi@eecs.umich.edu cmd = ['FMM'] 1174403Srdreslin@umich.edu if str(options.numcpus) == '1': 1184403Srdreslin@umich.edu input = options.rootdir + '/apps/fmm/inputs/input.2048' 1194403Srdreslin@umich.edu else: 1203360Srdreslin@umich.edu input = options.rootdir + '/apps/fmm/inputs/input.2048.p' + str(options.numcpus) 1214403Srdreslin@umich.edu cwd = options.rootdir + '/apps/fmm' 1223358Srdreslin@umich.edu 1233358Srdreslin@umich.educlass Ocean_contig(LiveProcess): 1244403Srdreslin@umich.edu executable = options.rootdir + '/apps/ocean/contiguous_partitions/OCEAN' 1255255Ssaidi@eecs.umich.edu cmd = ['OCEAN', '-p', str(options.numcpus)] 1264403Srdreslin@umich.edu cwd = options.rootdir + '/apps/ocean/contiguous_partitions' 1273358Srdreslin@umich.edu 1283358Srdreslin@umich.educlass Ocean_noncontig(LiveProcess): 1294403Srdreslin@umich.edu executable = options.rootdir + '/apps/ocean/non_contiguous_partitions/OCEAN' 1305255Ssaidi@eecs.umich.edu cmd = ['OCEAN', '-p', str(options.numcpus)] 1314403Srdreslin@umich.edu cwd = options.rootdir + '/apps/ocean/non_contiguous_partitions' 1323358Srdreslin@umich.edu 1333358Srdreslin@umich.educlass Raytrace(LiveProcess): 1344403Srdreslin@umich.edu executable = options.rootdir + '/apps/raytrace/RAYTRACE' 1355256Ssaidi@eecs.umich.edu cmd = ['RAYTRACE', '-p' + str(options.numcpus), 1365255Ssaidi@eecs.umich.edu options.rootdir + '/apps/raytrace/inputs/teapot.env'] 1374403Srdreslin@umich.edu cwd = options.rootdir + '/apps/raytrace' 1383358Srdreslin@umich.edu 1393358Srdreslin@umich.educlass Water_nsquared(LiveProcess): 1404403Srdreslin@umich.edu executable = options.rootdir + '/apps/water-nsquared/WATER-NSQUARED' 1415255Ssaidi@eecs.umich.edu cmd = ['WATER-NSQUARED'] 1424403Srdreslin@umich.edu if options.numcpus==1: 1434403Srdreslin@umich.edu input = options.rootdir + '/apps/water-nsquared/input' 1444403Srdreslin@umich.edu else: 1453360Srdreslin@umich.edu input = options.rootdir + '/apps/water-nsquared/input.p' + str(options.numcpus) 1464403Srdreslin@umich.edu cwd = options.rootdir + '/apps/water-nsquared' 1473358Srdreslin@umich.edu 1483358Srdreslin@umich.educlass Water_spatial(LiveProcess): 1494403Srdreslin@umich.edu executable = options.rootdir + '/apps/water-spatial/WATER-SPATIAL' 1505255Ssaidi@eecs.umich.edu cmd = ['WATER-SPATIAL'] 1514403Srdreslin@umich.edu if options.numcpus==1: 1524403Srdreslin@umich.edu input = options.rootdir + '/apps/water-spatial/input' 1534403Srdreslin@umich.edu else: 1543360Srdreslin@umich.edu input = options.rootdir + '/apps/water-spatial/input.p' + str(options.numcpus) 1554403Srdreslin@umich.edu cwd = options.rootdir + '/apps/water-spatial' 1563358Srdreslin@umich.edu 1573358Srdreslin@umich.edu# -------------------- 1583358Srdreslin@umich.edu# Base L1 Cache Definition 1593358Srdreslin@umich.edu# ==================== 1603358Srdreslin@umich.edu 1613358Srdreslin@umich.educlass L1(BaseCache): 1623358Srdreslin@umich.edu latency = options.l1latency 1633358Srdreslin@umich.edu block_size = 64 1643358Srdreslin@umich.edu mshrs = 12 1653358Srdreslin@umich.edu tgts_per_mshr = 8 1663358Srdreslin@umich.edu 1673358Srdreslin@umich.edu# ---------------------- 1683358Srdreslin@umich.edu# Base L2 Cache Definition 1693358Srdreslin@umich.edu# ---------------------- 1703358Srdreslin@umich.edu 1713358Srdreslin@umich.educlass L2(BaseCache): 1723358Srdreslin@umich.edu block_size = 64 1733358Srdreslin@umich.edu latency = options.l2latency 1743358Srdreslin@umich.edu mshrs = 92 1753358Srdreslin@umich.edu tgts_per_mshr = 16 1763358Srdreslin@umich.edu write_buffers = 8 1773358Srdreslin@umich.edu 1783358Srdreslin@umich.edu# ---------------------- 1793358Srdreslin@umich.edu# Define the cpus 1803358Srdreslin@umich.edu# ---------------------- 1813358Srdreslin@umich.edu 1823358Srdreslin@umich.edubusFrequency = Frequency(options.frequency) 1833358Srdreslin@umich.edu 1843358Srdreslin@umich.eduif options.timing: 1853358Srdreslin@umich.edu cpus = [TimingSimpleCPU(cpu_id = i, 1863358Srdreslin@umich.edu clock=options.frequency) 1873358Srdreslin@umich.edu for i in xrange(options.numcpus)] 1883358Srdreslin@umich.eduelif options.detailed: 1893358Srdreslin@umich.edu cpus = [DerivO3CPU(cpu_id = i, 1903358Srdreslin@umich.edu clock=options.frequency) 1913358Srdreslin@umich.edu for i in xrange(options.numcpus)] 1921516SN/Aelse: 1933358Srdreslin@umich.edu cpus = [AtomicSimpleCPU(cpu_id = i, 1943358Srdreslin@umich.edu clock=options.frequency) 1953358Srdreslin@umich.edu for i in xrange(options.numcpus)] 1961516SN/A 1973358Srdreslin@umich.edu# ---------------------- 1983358Srdreslin@umich.edu# Create a system, and add system wide objects 1993358Srdreslin@umich.edu# ---------------------- 2003358Srdreslin@umich.edusystem = System(cpu = cpus, physmem = PhysicalMemory(), 2013358Srdreslin@umich.edu membus = Bus(clock = busFrequency)) 2021516SN/A 2033358Srdreslin@umich.edusystem.toL2bus = Bus(clock = busFrequency) 2043358Srdreslin@umich.edusystem.l2 = L2(size = options.l2size, assoc = 8) 2053358Srdreslin@umich.edu 2063358Srdreslin@umich.edu# ---------------------- 2073358Srdreslin@umich.edu# Connect the L2 cache and memory together 2083358Srdreslin@umich.edu# ---------------------- 2093358Srdreslin@umich.edu 2103358Srdreslin@umich.edusystem.physmem.port = system.membus.port 2113358Srdreslin@umich.edusystem.l2.cpu_side = system.toL2bus.port 2123358Srdreslin@umich.edusystem.l2.mem_side = system.membus.port 2133358Srdreslin@umich.edu 2143358Srdreslin@umich.edu# ---------------------- 2153358Srdreslin@umich.edu# Connect the L2 cache and clusters together 2163358Srdreslin@umich.edu# ---------------------- 2173358Srdreslin@umich.edufor cpu in cpus: 2183358Srdreslin@umich.edu cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1), 2193358Srdreslin@umich.edu L1(size = options.l1size, assoc = 4)) 2203358Srdreslin@umich.edu cpu.mem = cpu.dcache 2213358Srdreslin@umich.edu # connect cpu level-1 caches to shared level-2 cache 2223358Srdreslin@umich.edu cpu.connectMemPorts(system.toL2bus) 2233358Srdreslin@umich.edu 2243358Srdreslin@umich.edu 2253358Srdreslin@umich.edu# ---------------------- 2263358Srdreslin@umich.edu# Define the root 2273358Srdreslin@umich.edu# ---------------------- 2283358Srdreslin@umich.edu 2293358Srdreslin@umich.eduroot = Root(system = system) 2303358Srdreslin@umich.edu 2313358Srdreslin@umich.edu# -------------------- 2323358Srdreslin@umich.edu# Pick the correct Splash2 Benchmarks 2333358Srdreslin@umich.edu# ==================== 2343358Srdreslin@umich.eduif options.benchmark == 'Cholesky': 2353358Srdreslin@umich.edu root.workload = Cholesky() 2363358Srdreslin@umich.eduelif options.benchmark == 'FFT': 2373358Srdreslin@umich.edu root.workload = FFT() 2383358Srdreslin@umich.eduelif options.benchmark == 'LUContig': 2393358Srdreslin@umich.edu root.workload = LU_contig() 2403358Srdreslin@umich.eduelif options.benchmark == 'LUNoncontig': 2413358Srdreslin@umich.edu root.workload = LU_noncontig() 2423358Srdreslin@umich.eduelif options.benchmark == 'Radix': 2433358Srdreslin@umich.edu root.workload = Radix() 2443358Srdreslin@umich.eduelif options.benchmark == 'Barnes': 2453358Srdreslin@umich.edu root.workload = Barnes() 2463358Srdreslin@umich.eduelif options.benchmark == 'FMM': 2473358Srdreslin@umich.edu root.workload = FMM() 2483358Srdreslin@umich.eduelif options.benchmark == 'OceanContig': 2493358Srdreslin@umich.edu root.workload = Ocean_contig() 2503358Srdreslin@umich.eduelif options.benchmark == 'OceanNoncontig': 2513358Srdreslin@umich.edu root.workload = Ocean_noncontig() 2523358Srdreslin@umich.eduelif options.benchmark == 'Raytrace': 2533358Srdreslin@umich.edu root.workload = Raytrace() 2543358Srdreslin@umich.eduelif options.benchmark == 'WaterNSquared': 2553358Srdreslin@umich.edu root.workload = Water_nsquared() 2563358Srdreslin@umich.eduelif options.benchmark == 'WaterSpatial': 2573358Srdreslin@umich.edu root.workload = Water_spatial() 2581516SN/Aelse: 2595256Ssaidi@eecs.umich.edu print >> sys.stderr, """The --benchmark environment variable was set to something improper. 2605256Ssaidi@eecs.umich.eduUse Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig, 2615256Ssaidi@eecs.umich.eduOceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial""" 2625256Ssaidi@eecs.umich.edu sys.exit(1) 2633358Srdreslin@umich.edu 2643358Srdreslin@umich.edu# -------------------- 2653358Srdreslin@umich.edu# Assign the workload to the cpus 2663358Srdreslin@umich.edu# ==================== 2673358Srdreslin@umich.edu 2683358Srdreslin@umich.edufor cpu in cpus: 2693358Srdreslin@umich.edu cpu.workload = root.workload 2703358Srdreslin@umich.edu 2713358Srdreslin@umich.edu# ---------------------- 2723358Srdreslin@umich.edu# Run the simulation 2733358Srdreslin@umich.edu# ---------------------- 2743358Srdreslin@umich.edu 2753358Srdreslin@umich.eduif options.timing or options.detailed: 2763358Srdreslin@umich.edu root.system.mem_mode = 'timing' 2773358Srdreslin@umich.edu 2783358Srdreslin@umich.edu# instantiate configuration 2797525Ssteve.reinhardt@amd.comm5.instantiate() 2803358Srdreslin@umich.edu 2813358Srdreslin@umich.edu# simulate until program terminates 2823358Srdreslin@umich.eduif options.maxtick: 2833358Srdreslin@umich.edu exit_event = m5.simulate(options.maxtick) 2843358Srdreslin@umich.eduelse: 2853646Srdreslin@umich.edu exit_event = m5.simulate(m5.MaxTick) 2863358Srdreslin@umich.edu 2873358Srdreslin@umich.eduprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 2883358Srdreslin@umich.edu 289