run.py revision 3358
12810SN/A# Copyright (c) 2005-2006 The Regents of The University of Michigan
29663Suri.wiener@arm.com# All rights reserved.
39663Suri.wiener@arm.com#
49663Suri.wiener@arm.com# Redistribution and use in source and binary forms, with or without
59663Suri.wiener@arm.com# modification, are permitted provided that the following conditions are
69663Suri.wiener@arm.com# met: redistributions of source code must retain the above copyright
79663Suri.wiener@arm.com# notice, this list of conditions and the following disclaimer;
89663Suri.wiener@arm.com# redistributions in binary form must reproduce the above copyright
99663Suri.wiener@arm.com# notice, this list of conditions and the following disclaimer in the
109663Suri.wiener@arm.com# documentation and/or other materials provided with the distribution;
119663Suri.wiener@arm.com# neither the name of the copyright holders nor the names of its
129663Suri.wiener@arm.com# contributors may be used to endorse or promote products derived from
139663Suri.wiener@arm.com# this software without specific prior written permission.
142810SN/A#
157636Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
162810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
172810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
182810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
192810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
202810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
212810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
222810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
232810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
242810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
252810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
262810SN/A#
272810SN/A# Authors: Ron Dreslinski
282810SN/A
292810SN/A# Splash2 Run Script
302810SN/A#
312810SN/A
322810SN/Aimport m5
332810SN/Afrom m5.objects import *
342810SN/Aimport os, optparse, sys
352810SN/Am5.AddToPath('../common')
362810SN/A
372810SN/A# --------------------
382810SN/A# Define Command Line Options
392810SN/A# ====================
402810SN/A
412810SN/Aparser = optparse.OptionParser()
422810SN/A
432810SN/Aparser.add_option("-d", "--detailed", action="store_true")
442810SN/Aparser.add_option("-t", "--timing", action="store_true")
452810SN/Aparser.add_option("-m", "--maxtick", type="int")
462810SN/Aparser.add_option("-n", "--numcpus",
472810SN/A                  help="Number of cpus in total", type="int")
482810SN/Aparser.add_option("-f", "--frequency",
492810SN/A                  help="Frequency of each CPU")
506216Snate@binkert.orgparser.add_option("-p", "--protocol",
516216Snate@binkert.org                  default="moesi",
522810SN/A                  help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)")
532810SN/Aparser.add_option("--l1size")
542810SN/Aparser.add_option("--l1latency")
556216Snate@binkert.orgparser.add_option("--l2size")
566216Snate@binkert.orgparser.add_option("--l2latency")
578232Snate@binkert.orgparser.add_option("--rootdir",
586216Snate@binkert.org                  help="ROot directory of Splash2",
595338Sstever@gmail.com                  default="../../Splash2/codes")
606216Snate@binkert.orgparser.add_option("-b", "--benchmark",
612810SN/A                  help="Splash 2 benchmark to run")
622810SN/A
632810SN/A(options, args) = parser.parse_args()
649725Sandreas.hansson@arm.com
659725Sandreas.hansson@arm.comif args:
669725Sandreas.hansson@arm.com    print "Error: script doesn't take any positional arguments"
679725Sandreas.hansson@arm.com    sys.exit(1)
689725Sandreas.hansson@arm.com
692810SN/A# --------------------
702810SN/A# Define Splash2 Benchmarks
712810SN/A# ====================
724903SN/Aclass Cholesky(LiveProcess):
734903SN/A        executable = options.rootdir + '/kernels/cholesky/CHOLESKY'
744903SN/A        cmd = 'CHOLESKY -p' + str(options.numcpus) + ' '\
754903SN/A             + options.rootdir + '/kernels/cholesky/inputs/tk23.O'
764903SN/A
774903SN/Aclass FFT(LiveProcess):
784903SN/A        executable = options.rootdir + 'kernels/fft/FFT'
794908SN/A        cmd = 'FFT -p' + str(options.numcpus) + ' -m18'
805875Ssteve.reinhardt@amd.com
814903SN/Aclass LU_contig(LiveProcess):
825875Ssteve.reinhardt@amd.com        executable = options.rootdir + 'kernels/lu/contiguous_blocks/LU'
834903SN/A        cmd = 'LU -p' + str(options.numcpus)
844903SN/A
854903SN/Aclass LU_noncontig(LiveProcess):
864903SN/A        executable = options.rootdir + 'kernels/lu/non_contiguous_blocks/LU'
877669Ssteve.reinhardt@amd.com        cmd = 'LU -p' + str(options.numcpus)
887669Ssteve.reinhardt@amd.com
897669Ssteve.reinhardt@amd.comclass Radix(LiveProcess):
907669Ssteve.reinhardt@amd.com        executable = options.rootdir + 'kernels/radix/RADIX'
914903SN/A        cmd = 'RADIX -n524288 -p' + str(options.numcpus)
924903SN/A
935318SN/Aclass Barnes(LiveProcess):
944908SN/A        executable = options.rootdir + 'apps/barnes/BARNES'
955318SN/A        cmd = 'BARNES'
969543Ssascha.bischoff@arm.com        input = options.rootdir + 'apps/barnes/input.p' + str(options.numcpus)
979543Ssascha.bischoff@arm.com
989543Ssascha.bischoff@arm.comclass FMM(LiveProcess):
999543Ssascha.bischoff@arm.com        executable = options.rootdir + 'apps/fmm/FMM'
1004908SN/A        cmd = 'FMM'
1014908SN/A        input = options.rootdir + 'apps/fmm/inputs/input.2048.p' + str(options.numcpus)
1024908SN/A
1034908SN/Aclass Ocean_contig(LiveProcess):
1044903SN/A        executable = options.rootdir + 'apps/ocean/contiguous_partitions/OCEAN'
1054903SN/A        cmd = 'OCEAN -p' + str(options.numcpus)
1065875Ssteve.reinhardt@amd.com
1074903SN/Aclass Ocean_noncontig(LiveProcess):
1084903SN/A        executable = options.rootdir + 'apps/ocean/non_contiguous_partitions/OCEAN'
1094903SN/A        cmd = 'OCEAN -p' + str(options.numcpus)
1107667Ssteve.reinhardt@amd.com
1117667Ssteve.reinhardt@amd.comclass Raytrace(LiveProcess):
1127667Ssteve.reinhardt@amd.com        executable = options.rootdir + 'apps/raytrace/RAYTRACE'
1137667Ssteve.reinhardt@amd.com        cmd = 'RAYTRACE -p' + str(options.numcpus) + ' ' \
1147667Ssteve.reinhardt@amd.com             + options.rootdir + 'apps/raytrace/inputs/teapot.env'
1157667Ssteve.reinhardt@amd.com
1167667Ssteve.reinhardt@amd.comclass Water_nsquared(LiveProcess):
1177667Ssteve.reinhardt@amd.com        executable = options.rootdir + 'apps/water-nsquared/WATER-NSQUARED'
1187667Ssteve.reinhardt@amd.com        cmd = 'WATER-NSQUARED'
1197669Ssteve.reinhardt@amd.com        input = options.rootdir + 'apps/water-nsquared/input.p' + str(options.numcpus)
1207669Ssteve.reinhardt@amd.com
1217669Ssteve.reinhardt@amd.comclass Water_spatial(LiveProcess):
1227667Ssteve.reinhardt@amd.com        executable = options.rootdir + 'apps/water-spatial/WATER-SPATIAL'
1237667Ssteve.reinhardt@amd.com        cmd = 'WATER-SPATIAL'
1247667Ssteve.reinhardt@amd.com        input = options.rootdir + 'apps/water-spatial/input.p' + str(options.numcpus)
1257667Ssteve.reinhardt@amd.com
1264903SN/A
1274903SN/A# --------------------
1284903SN/A# Base L1 Cache Definition
1294903SN/A# ====================
1304903SN/A
1314903SN/Aclass L1(BaseCache):
1324903SN/A    latency = options.l1latency
1334903SN/A    block_size = 64
1347667Ssteve.reinhardt@amd.com    mshrs = 12
1354903SN/A    tgts_per_mshr = 8
1364903SN/A    protocol = CoherenceProtocol(protocol=options.protocol)
1374903SN/A
1384903SN/A# ----------------------
1394903SN/A# Base L2 Cache Definition
1404903SN/A# ----------------------
1412810SN/A
1424908SN/Aclass L2(BaseCache):
1434908SN/A    block_size = 64
1444908SN/A    latency = options.l2latency
1454908SN/A    mshrs = 92
1465318SN/A    tgts_per_mshr = 16
1479543Ssascha.bischoff@arm.com    write_buffers = 8
1489543Ssascha.bischoff@arm.com
1499543Ssascha.bischoff@arm.com# ----------------------
1509543Ssascha.bischoff@arm.com# Define the cpus
1519543Ssascha.bischoff@arm.com# ----------------------
1529543Ssascha.bischoff@arm.com
1539543Ssascha.bischoff@arm.combusFrequency = Frequency(options.frequency)
1545318SN/A
1555318SN/Aif options.timing:
1565318SN/A    cpus = [TimingSimpleCPU(cpu_id = i,
1574908SN/A                            clock=options.frequency)
1584908SN/A            for i in xrange(options.numcpus)]
1594908SN/Aelif options.detailed:
1604908SN/A    cpus = [DerivO3CPU(cpu_id = i,
1614908SN/A                       clock=options.frequency)
1624920SN/A            for i in xrange(options.numcpus)]
1634920SN/Aelse:
1644920SN/A    cpus = [AtomicSimpleCPU(cpu_id = i,
1654920SN/A                            clock=options.frequency)
1664920SN/A            for i in xrange(options.numcpus)]
1674920SN/A
1684920SN/A# ----------------------
1694920SN/A# Create a system, and add system wide objects
1704920SN/A# ----------------------
1714920SN/Asystem = System(cpu = cpus, physmem = PhysicalMemory(),
1724920SN/A                membus = Bus(clock = busFrequency))
1734920SN/A
1744920SN/Asystem.toL2bus = Bus(clock = busFrequency)
1754920SN/Asystem.l2 = L2(size = options.l2size, assoc = 8)
1764908SN/A
1775314SN/A# ----------------------
1785314SN/A# Connect the L2 cache and memory together
1795314SN/A# ----------------------
1805314SN/A
1815314SN/Asystem.physmem.port = system.membus.port
1825875Ssteve.reinhardt@amd.comsystem.l2.cpu_side = system.toL2bus.port
1835875Ssteve.reinhardt@amd.comsystem.l2.mem_side = system.membus.port
1848988SAli.Saidi@ARM.com
1858988SAli.Saidi@ARM.com# ----------------------
1868988SAli.Saidi@ARM.com# Connect the L2 cache and clusters together
1878988SAli.Saidi@ARM.com# ----------------------
1888988SAli.Saidi@ARM.comfor cpu in cpus:
1898988SAli.Saidi@ARM.com    cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
1908988SAli.Saidi@ARM.com                                L1(size = options.l1size, assoc = 4))
1918988SAli.Saidi@ARM.com    cpu.mem = cpu.dcache
1928988SAli.Saidi@ARM.com    # connect cpu level-1 caches to shared level-2 cache
1938988SAli.Saidi@ARM.com    cpu.connectMemPorts(system.toL2bus)
1948988SAli.Saidi@ARM.com
1958988SAli.Saidi@ARM.com
1965875Ssteve.reinhardt@amd.com# ----------------------
1975875Ssteve.reinhardt@amd.com# Define the root
1985314SN/A# ----------------------
1995314SN/A
2005314SN/Aroot = Root(system = system)
2015314SN/A
2025314SN/A# --------------------
2035314SN/A# Pick the correct Splash2 Benchmarks
2044666SN/A# ====================
2054871SN/Aif options.benchmark == 'Cholesky':
2062810SN/A    root.workload = Cholesky()
2072885SN/Aelif options.benchmark == 'FFT':
2084626SN/A    root.workload = FFT()
2094871SN/Aelif options.benchmark == 'LUContig':
2104666SN/A    root.workload = LU_contig()
2114626SN/Aelif options.benchmark == 'LUNoncontig':
2125730SSteve.Reinhardt@amd.com    root.workload = LU_noncontig()
2134626SN/Aelif options.benchmark == 'Radix':
2144626SN/A    root.workload = Radix()
2154908SN/Aelif options.benchmark == 'Barnes':
2164626SN/A    root.workload = Barnes()
2179725Sandreas.hansson@arm.comelif options.benchmark == 'FMM':
2184626SN/A    root.workload = FMM()
2195875Ssteve.reinhardt@amd.comelif options.benchmark == 'OceanContig':
2205875Ssteve.reinhardt@amd.com    root.workload = Ocean_contig()
2215875Ssteve.reinhardt@amd.comelif options.benchmark == 'OceanNoncontig':
2229725Sandreas.hansson@arm.com    root.workload = Ocean_noncontig()
2239725Sandreas.hansson@arm.comelif options.benchmark == 'Raytrace':
2244668SN/A    root.workload = Raytrace()
2252810SN/Aelif options.benchmark == 'WaterNSquared':
2262810SN/A    root.workload = Water_nsquared()
2274908SN/Aelif options.benchmark == 'WaterSpatial':
2285318SN/A    root.workload = Water_spatial()
2295318SN/Aelse:
2305318SN/A    panic("The --benchmark environment variable was set to something" \
2315318SN/A          +" improper.\nUse Cholesky, FFT, LUContig, LUNoncontig, Radix" \
2325318SN/A          +", Barnes, FMM, OceanContig,\nOceanNoncontig, Raytrace," \
2335318SN/A          +" WaterNSquared, or WaterSpatial\n")
2345318SN/A
2359725Sandreas.hansson@arm.com# --------------------
2365318SN/A# Assign the workload to the cpus
2375318SN/A# ====================
2384908SN/A
2397667Ssteve.reinhardt@amd.comfor cpu in cpus:
2404908SN/A    cpu.workload = root.workload
2414908SN/A
2425730SSteve.Reinhardt@amd.com# ----------------------
2434908SN/A# Run the simulation
2444908SN/A# ----------------------
2454908SN/A
2464908SN/Aif options.timing or options.detailed:
2474908SN/A    root.system.mem_mode = 'timing'
2484908SN/A
2494908SN/A# instantiate configuration
2509725Sandreas.hansson@arm.comm5.instantiate(root)
2517667Ssteve.reinhardt@amd.com
2527667Ssteve.reinhardt@amd.com# simulate until program terminates
2537667Ssteve.reinhardt@amd.comif options.maxtick:
2544908SN/A    exit_event = m5.simulate(options.maxtick)
2554908SN/Aelse:
2564908SN/A    exit_event = m5.simulate()
2579725Sandreas.hansson@arm.com
2584908SN/Aprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
2594908SN/A
2604908SN/A