run.py revision 10720
12381SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan
212342Snikos.nikoleris@arm.com# All rights reserved.
38711Sandreas.hansson@arm.com#
48711Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without
58711Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are
68711Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright
78711Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer;
88711Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright
98711Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the
108711Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution;
118711Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its
128711Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from
138711Sandreas.hansson@arm.com# this software without specific prior written permission.
142381SN/A#
152381SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
162381SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
172381SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
182381SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
192381SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
202381SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
212381SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
222381SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
232381SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
242381SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
252381SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
262381SN/A#
272381SN/A# Authors: Ron Dreslinski
282381SN/A
292381SN/A# Splash2 Run Script
302381SN/A#
312381SN/A
322381SN/Aimport os
332381SN/Aimport optparse
342381SN/Aimport sys
352381SN/A
362381SN/Aimport m5
372381SN/Afrom m5.objects import *
382381SN/A
392665Ssaidi@eecs.umich.edum5.util.addToPath('../common')
402665Ssaidi@eecs.umich.edu
418853Sandreas.hansson@arm.com# --------------------
428922Swilliam.wang@arm.com# Define Command Line Options
432381SN/A# ====================
442381SN/A
452381SN/Aparser = optparse.OptionParser()
462381SN/A
478922Swilliam.wang@arm.comparser.add_option("-d", "--detailed", action="store_true")
482381SN/Aparser.add_option("-t", "--timing", action="store_true")
492381SN/Aparser.add_option("-m", "--maxtick", type="int")
502381SN/Aparser.add_option("-n", "--numcpus",
512381SN/A                  help="Number of cpus in total", type="int")
522381SN/Aparser.add_option("-f", "--frequency",
539235Sandreas.hansson@arm.com                  default = "1GHz",
5413845Sgabeblack@google.com                  help="Frequency of each CPU")
552381SN/Aparser.add_option("--l1size",
5613771Sgabeblack@google.com                  default = "32kB")
572381SN/Aparser.add_option("--l1latency",
5813892Sgabeblack@google.com                  default = "1ns")
593401Sktlim@umich.eduparser.add_option("--l2size",
608922Swilliam.wang@arm.com                  default = "256kB")
619294Sandreas.hansson@arm.comparser.add_option("--l2latency",
629294Sandreas.hansson@arm.com                  default = "10ns")
639294Sandreas.hansson@arm.comparser.add_option("--rootdir",
649294Sandreas.hansson@arm.com                  help="Root directory of Splash2",
659294Sandreas.hansson@arm.com                  default="/dist/splash2/codes")
669294Sandreas.hansson@arm.comparser.add_option("-b", "--benchmark",
679294Sandreas.hansson@arm.com                  help="Splash 2 benchmark to run")
689294Sandreas.hansson@arm.com
699294Sandreas.hansson@arm.com(options, args) = parser.parse_args()
709294Sandreas.hansson@arm.com
719294Sandreas.hansson@arm.comif args:
729294Sandreas.hansson@arm.com    print "Error: script doesn't take any positional arguments"
739294Sandreas.hansson@arm.com    sys.exit(1)
749294Sandreas.hansson@arm.com
759294Sandreas.hansson@arm.comif not options.numcpus:
7613769Sgabeblack@google.com    print "Specify the number of cpus with -n"
779294Sandreas.hansson@arm.com    sys.exit(1)
789294Sandreas.hansson@arm.com
799294Sandreas.hansson@arm.com# --------------------
809294Sandreas.hansson@arm.com# Define Splash2 Benchmarks
819294Sandreas.hansson@arm.com# ====================
829294Sandreas.hansson@arm.comclass Cholesky(LiveProcess):
839294Sandreas.hansson@arm.com    cwd = options.rootdir + '/kernels/cholesky'
849294Sandreas.hansson@arm.com    executable = options.rootdir + '/kernels/cholesky/CHOLESKY'
859294Sandreas.hansson@arm.com    cmd = ['CHOLESKY', '-p' +  str(options.numcpus),
869294Sandreas.hansson@arm.com            options.rootdir + '/kernels/cholesky/inputs/tk23.O']
879294Sandreas.hansson@arm.com
889294Sandreas.hansson@arm.comclass FFT(LiveProcess):
899294Sandreas.hansson@arm.com    cwd = options.rootdir + '/kernels/fft'
909294Sandreas.hansson@arm.com    executable = options.rootdir + '/kernels/fft/FFT'
919294Sandreas.hansson@arm.com    cmd = ['FFT', '-p', str(options.numcpus), '-m18']
929294Sandreas.hansson@arm.com
939294Sandreas.hansson@arm.comclass LU_contig(LiveProcess):
949294Sandreas.hansson@arm.com    executable = options.rootdir + '/kernels/lu/contiguous_blocks/LU'
959294Sandreas.hansson@arm.com    cmd = ['LU', '-p', str(options.numcpus)]
9613769Sgabeblack@google.com    cwd = options.rootdir + '/kernels/lu/contiguous_blocks'
979294Sandreas.hansson@arm.com
989294Sandreas.hansson@arm.comclass LU_noncontig(LiveProcess):
999294Sandreas.hansson@arm.com    executable = options.rootdir + '/kernels/lu/non_contiguous_blocks/LU'
1009294Sandreas.hansson@arm.com    cmd = ['LU', '-p', str(options.numcpus)]
1019294Sandreas.hansson@arm.com    cwd = options.rootdir + '/kernels/lu/non_contiguous_blocks'
1029294Sandreas.hansson@arm.com
1039294Sandreas.hansson@arm.comclass Radix(LiveProcess):
1049294Sandreas.hansson@arm.com    executable = options.rootdir + '/kernels/radix/RADIX'
1059294Sandreas.hansson@arm.com    cmd = ['RADIX', '-n524288', '-p', str(options.numcpus)]
1068922Swilliam.wang@arm.com    cwd = options.rootdir + '/kernels/radix'
1078922Swilliam.wang@arm.com
1088922Swilliam.wang@arm.comclass Barnes(LiveProcess):
1099294Sandreas.hansson@arm.com    executable = options.rootdir + '/apps/barnes/BARNES'
1109294Sandreas.hansson@arm.com    cmd = ['BARNES']
1119294Sandreas.hansson@arm.com    input = options.rootdir + '/apps/barnes/input.p' + str(options.numcpus)
1129294Sandreas.hansson@arm.com    cwd = options.rootdir + '/apps/barnes'
1139294Sandreas.hansson@arm.com
1148922Swilliam.wang@arm.comclass FMM(LiveProcess):
1159294Sandreas.hansson@arm.com    executable = options.rootdir + '/apps/fmm/FMM'
1168922Swilliam.wang@arm.com    cmd = ['FMM']
1178922Swilliam.wang@arm.com    if str(options.numcpus) == '1':
1188975Sandreas.hansson@arm.com        input = options.rootdir + '/apps/fmm/inputs/input.2048'
1198975Sandreas.hansson@arm.com    else:
1208922Swilliam.wang@arm.com        input = options.rootdir + '/apps/fmm/inputs/input.2048.p' + str(options.numcpus)
1218922Swilliam.wang@arm.com    cwd = options.rootdir + '/apps/fmm'
1228922Swilliam.wang@arm.com
1238922Swilliam.wang@arm.comclass Ocean_contig(LiveProcess):
12413769Sgabeblack@google.com    executable = options.rootdir + '/apps/ocean/contiguous_partitions/OCEAN'
12513769Sgabeblack@google.com    cmd = ['OCEAN', '-p', str(options.numcpus)]
12613892Sgabeblack@google.com    cwd = options.rootdir + '/apps/ocean/contiguous_partitions'
12713769Sgabeblack@google.com
1288922Swilliam.wang@arm.comclass Ocean_noncontig(LiveProcess):
1298922Swilliam.wang@arm.com    executable = options.rootdir + '/apps/ocean/non_contiguous_partitions/OCEAN'
13013892Sgabeblack@google.com    cmd = ['OCEAN', '-p', str(options.numcpus)]
13113769Sgabeblack@google.com    cwd = options.rootdir + '/apps/ocean/non_contiguous_partitions'
1328922Swilliam.wang@arm.com
1338922Swilliam.wang@arm.comclass Raytrace(LiveProcess):
1349178Sandreas.hansson@arm.com    executable = options.rootdir + '/apps/raytrace/RAYTRACE'
1359178Sandreas.hansson@arm.com    cmd = ['RAYTRACE', '-p' + str(options.numcpus),
1369178Sandreas.hansson@arm.com           options.rootdir + '/apps/raytrace/inputs/teapot.env']
1379178Sandreas.hansson@arm.com    cwd = options.rootdir + '/apps/raytrace'
13813782Sgabeblack@google.com
1399178Sandreas.hansson@arm.comclass Water_nsquared(LiveProcess):
1409178Sandreas.hansson@arm.com    executable = options.rootdir + '/apps/water-nsquared/WATER-NSQUARED'
1419178Sandreas.hansson@arm.com    cmd = ['WATER-NSQUARED']
1429178Sandreas.hansson@arm.com    if options.numcpus==1:
14313782Sgabeblack@google.com        input = options.rootdir + '/apps/water-nsquared/input'
1449178Sandreas.hansson@arm.com    else:
1458922Swilliam.wang@arm.com        input = options.rootdir + '/apps/water-nsquared/input.p' + str(options.numcpus)
1468948Sandreas.hansson@arm.com    cwd = options.rootdir + '/apps/water-nsquared'
1478948Sandreas.hansson@arm.com
1488948Sandreas.hansson@arm.comclass Water_spatial(LiveProcess):
1498948Sandreas.hansson@arm.com    executable = options.rootdir + '/apps/water-spatial/WATER-SPATIAL'
1508948Sandreas.hansson@arm.com    cmd = ['WATER-SPATIAL']
1518948Sandreas.hansson@arm.com    if options.numcpus==1:
1528948Sandreas.hansson@arm.com        input = options.rootdir + '/apps/water-spatial/input'
1538948Sandreas.hansson@arm.com    else:
1548948Sandreas.hansson@arm.com        input = options.rootdir + '/apps/water-spatial/input.p' + str(options.numcpus)
1558948Sandreas.hansson@arm.com    cwd = options.rootdir + '/apps/water-spatial'
1568948Sandreas.hansson@arm.com
15713845Sgabeblack@google.com# --------------------
15813845Sgabeblack@google.com# Base L1 Cache Definition
15913845Sgabeblack@google.com# ====================
16013845Sgabeblack@google.com
16113845Sgabeblack@google.comclass L1(BaseCache):
16213845Sgabeblack@google.com    latency = options.l1latency
16313845Sgabeblack@google.com    mshrs = 12
16413845Sgabeblack@google.com    tgts_per_mshr = 8
16513845Sgabeblack@google.com
16613845Sgabeblack@google.com# ----------------------
16713845Sgabeblack@google.com# Base L2 Cache Definition
16813845Sgabeblack@google.com# ----------------------
1698948Sandreas.hansson@arm.com
1708948Sandreas.hansson@arm.comclass L2(BaseCache):
1718948Sandreas.hansson@arm.com    latency = options.l2latency
1728948Sandreas.hansson@arm.com    mshrs = 92
1738948Sandreas.hansson@arm.com    tgts_per_mshr = 16
1748948Sandreas.hansson@arm.com    write_buffers = 8
1758948Sandreas.hansson@arm.com
1768948Sandreas.hansson@arm.com# ----------------------
1778948Sandreas.hansson@arm.com# Define the cpus
1788975Sandreas.hansson@arm.com# ----------------------
1798975Sandreas.hansson@arm.com
1808975Sandreas.hansson@arm.combusFrequency = Frequency(options.frequency)
18110713Sandreas.hansson@arm.com
1828975Sandreas.hansson@arm.comif options.timing:
1838975Sandreas.hansson@arm.com    cpus = [TimingSimpleCPU(cpu_id = i,
1848975Sandreas.hansson@arm.com                            clock=options.frequency)
1858975Sandreas.hansson@arm.com            for i in xrange(options.numcpus)]
1868975Sandreas.hansson@arm.comelif options.detailed:
1878975Sandreas.hansson@arm.com    cpus = [DerivO3CPU(cpu_id = i,
1888975Sandreas.hansson@arm.com                       clock=options.frequency)
1898948Sandreas.hansson@arm.com            for i in xrange(options.numcpus)]
1908948Sandreas.hansson@arm.comelse:
19112342Snikos.nikoleris@arm.com    cpus = [AtomicSimpleCPU(cpu_id = i,
19212342Snikos.nikoleris@arm.com                            clock=options.frequency)
19312342Snikos.nikoleris@arm.com            for i in xrange(options.numcpus)]
19412342Snikos.nikoleris@arm.com
19512342Snikos.nikoleris@arm.com# ----------------------
19612342Snikos.nikoleris@arm.com# Create a system, and add system wide objects
19712342Snikos.nikoleris@arm.com# ----------------------
19812342Snikos.nikoleris@arm.comsystem = System(cpu = cpus, physmem = SimpleMemory(),
19912342Snikos.nikoleris@arm.com                membus = SystemXBar(clock = busFrequency))
20012342Snikos.nikoleris@arm.comsystem.clock = '1GHz'
20112342Snikos.nikoleris@arm.com
20212342Snikos.nikoleris@arm.comsystem.toL2bus = L2XBar(clock = busFrequency)
20312342Snikos.nikoleris@arm.comsystem.l2 = L2(size = options.l2size, assoc = 8)
2048975Sandreas.hansson@arm.com
2058975Sandreas.hansson@arm.com# ----------------------
2068975Sandreas.hansson@arm.com# Connect the L2 cache and memory together
20710713Sandreas.hansson@arm.com# ----------------------
20810713Sandreas.hansson@arm.com
2098975Sandreas.hansson@arm.comsystem.physmem.port = system.membus.master
2108975Sandreas.hansson@arm.comsystem.l2.cpu_side = system.toL2bus.master
2118948Sandreas.hansson@arm.comsystem.l2.mem_side = system.membus.slave
2128975Sandreas.hansson@arm.comsystem.system_port = system.membus.slave
2138922Swilliam.wang@arm.com
2148922Swilliam.wang@arm.com# ----------------------
2159087Sandreas.hansson@arm.com# Connect the L2 cache and clusters together
21610713Sandreas.hansson@arm.com# ----------------------
21710713Sandreas.hansson@arm.comfor cpu in cpus:
21810713Sandreas.hansson@arm.com    cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
2199087Sandreas.hansson@arm.com                                L1(size = options.l1size, assoc = 4))
22010713Sandreas.hansson@arm.com    # connect cpu level-1 caches to shared level-2 cache
2219087Sandreas.hansson@arm.com    cpu.connectAllPorts(system.toL2bus, system.membus)
2229087Sandreas.hansson@arm.com
2238922Swilliam.wang@arm.com
2248711Sandreas.hansson@arm.com# ----------------------
2258922Swilliam.wang@arm.com# Define the root
2268922Swilliam.wang@arm.com# ----------------------
2278922Swilliam.wang@arm.com
2288711Sandreas.hansson@arm.comroot = Root(full_system = False, system = system)
2298711Sandreas.hansson@arm.com
2308711Sandreas.hansson@arm.com# --------------------
2318922Swilliam.wang@arm.com# Pick the correct Splash2 Benchmarks
2322381SN/A# ====================
2338711Sandreas.hansson@arm.comif options.benchmark == 'Cholesky':
2349089Sandreas.hansson@arm.com    root.workload = Cholesky()
2359089Sandreas.hansson@arm.comelif options.benchmark == 'FFT':
2369089Sandreas.hansson@arm.com    root.workload = FFT()
2379089Sandreas.hansson@arm.comelif options.benchmark == 'LUContig':
2385314Sstever@gmail.com    root.workload = LU_contig()
2395314Sstever@gmail.comelif options.benchmark == 'LUNoncontig':
2405314Sstever@gmail.com    root.workload = LU_noncontig()
2415314Sstever@gmail.comelif options.benchmark == 'Radix':
2428975Sandreas.hansson@arm.com    root.workload = Radix()
2438975Sandreas.hansson@arm.comelif options.benchmark == 'Barnes':
2448975Sandreas.hansson@arm.com    root.workload = Barnes()
2458975Sandreas.hansson@arm.comelif options.benchmark == 'FMM':
2468975Sandreas.hansson@arm.com    root.workload = FMM()
2478975Sandreas.hansson@arm.comelif options.benchmark == 'OceanContig':
2488975Sandreas.hansson@arm.com    root.workload = Ocean_contig()
2498975Sandreas.hansson@arm.comelif options.benchmark == 'OceanNoncontig':
2508975Sandreas.hansson@arm.com    root.workload = Ocean_noncontig()
2518975Sandreas.hansson@arm.comelif options.benchmark == 'Raytrace':
2528975Sandreas.hansson@arm.com    root.workload = Raytrace()
2538975Sandreas.hansson@arm.comelif options.benchmark == 'WaterNSquared':
2548975Sandreas.hansson@arm.com    root.workload = Water_nsquared()
2558975Sandreas.hansson@arm.comelif options.benchmark == 'WaterSpatial':
2568975Sandreas.hansson@arm.com    root.workload = Water_spatial()
2578975Sandreas.hansson@arm.comelse:
2588975Sandreas.hansson@arm.com    print >> sys.stderr, """The --benchmark environment variable was set to something improper.
2598975Sandreas.hansson@arm.comUse Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig,
2608975Sandreas.hansson@arm.comOceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial"""
2618975Sandreas.hansson@arm.com    sys.exit(1)
2628975Sandreas.hansson@arm.com
2638975Sandreas.hansson@arm.com# --------------------
2648975Sandreas.hansson@arm.com# Assign the workload to the cpus
2658975Sandreas.hansson@arm.com# ====================
2668975Sandreas.hansson@arm.com
2678975Sandreas.hansson@arm.comfor cpu in cpus:
2688975Sandreas.hansson@arm.com    cpu.workload = root.workload
2698975Sandreas.hansson@arm.com
2708975Sandreas.hansson@arm.com# ----------------------
2718975Sandreas.hansson@arm.com# Run the simulation
2728975Sandreas.hansson@arm.com# ----------------------
2738975Sandreas.hansson@arm.com
2748975Sandreas.hansson@arm.comif options.timing or options.detailed:
2758975Sandreas.hansson@arm.com    root.system.mem_mode = 'timing'
27610713Sandreas.hansson@arm.com
27710713Sandreas.hansson@arm.com# instantiate configuration
27810713Sandreas.hansson@arm.comm5.instantiate()
2799087Sandreas.hansson@arm.com
28010713Sandreas.hansson@arm.com# simulate until program terminates
28110713Sandreas.hansson@arm.comif options.maxtick:
28210713Sandreas.hansson@arm.com    exit_event = m5.simulate(options.maxtick)
28310713Sandreas.hansson@arm.comelse:
28410713Sandreas.hansson@arm.com    exit_event = m5.simulate(m5.MaxTick)
28510713Sandreas.hansson@arm.com
28610713Sandreas.hansson@arm.comprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
28710713Sandreas.hansson@arm.com
28810713Sandreas.hansson@arm.com