Ruby.py revision 13980:62a28c423e91 
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# Copyright (c) 2009 Advanced Micro Devices, Inc.
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39#
40# Authors: Brad Beckmann
41
42from __future__ import print_function
43
44import math
45import m5
46from m5.objects import *
47from m5.defines import buildEnv
48from m5.util import addToPath, fatal
49
50addToPath('../')
51
52from common import MemConfig
53from common import FileSystemConfig
54
55from topologies import *
56from network import Network
57
58def define_options(parser):
59    # By default, ruby uses the simple timing cpu
60    parser.set_defaults(cpu_type="TimingSimpleCPU")
61
62    parser.add_option("--ruby-clock", action="store", type="string",
63                      default='2GHz',
64                      help="Clock for blocks running at Ruby system's speed")
65
66    parser.add_option("--access-backing-store", action="store_true", default=False,
67                      help="Should ruby maintain a second copy of memory")
68
69    # Options related to cache structure
70    parser.add_option("--ports", action="store", type="int", default=4,
71                      help="used of transitions per cycle which is a proxy \
72                            for the number of ports.")
73
74    # network options are in network/Network.py
75
76    # ruby mapping options
77    parser.add_option("--numa-high-bit", type="int", default=0,
78                      help="high order address bit to use for numa mapping. " \
79                           "0 = highest bit, not specified = lowest bit")
80
81    parser.add_option("--recycle-latency", type="int", default=10,
82                      help="Recycle latency for ruby controller input buffers")
83
84    protocol = buildEnv['PROTOCOL']
85    exec("from . import %s" % protocol)
86    eval("%s.define_options(parser)" % protocol)
87    Network.define_options(parser)
88
89def setup_memory_controllers(system, ruby, dir_cntrls, options):
90    ruby.block_size_bytes = options.cacheline_size
91    ruby.memory_size_bits = 48
92
93    index = 0
94    mem_ctrls = []
95    crossbars = []
96
97    if options.numa_high_bit:
98        dir_bits = int(math.log(options.num_dirs, 2))
99        intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1)
100    else:
101        # if the numa_bit is not specified, set the directory bits as the
102        # lowest bits above the block offset bits
103        intlv_size = options.cacheline_size
104
105    # Sets bits to be used for interleaving.  Creates memory controllers
106    # attached to a directory controller.  A separate controller is created
107    # for each address range as the abstract memory can handle only one
108    # contiguous address range as of now.
109    for dir_cntrl in dir_cntrls:
110        crossbar = None
111        if len(system.mem_ranges) > 1:
112            crossbar = IOXBar()
113            crossbars.append(crossbar)
114            dir_cntrl.memory = crossbar.slave
115
116        dir_ranges = []
117        for r in system.mem_ranges:
118            mem_ctrl = MemConfig.create_mem_ctrl(
119                MemConfig.get(options.mem_type), r, index, options.num_dirs,
120                int(math.log(options.num_dirs, 2)), intlv_size)
121
122            if options.access_backing_store:
123                mem_ctrl.kvm_map=False
124
125            mem_ctrls.append(mem_ctrl)
126            dir_ranges.append(mem_ctrl.range)
127
128            if crossbar != None:
129                mem_ctrl.port = crossbar.master
130            else:
131                mem_ctrl.port = dir_cntrl.memory
132
133        index += 1
134        dir_cntrl.addr_ranges = dir_ranges
135
136    system.mem_ctrls = mem_ctrls
137
138    if len(crossbars) > 0:
139        ruby.crossbars = crossbars
140
141
142def create_topology(controllers, options):
143    """ Called from create_system in configs/ruby/<protocol>.py
144        Must return an object which is a subclass of BaseTopology
145        found in configs/topologies/BaseTopology.py
146        This is a wrapper for the legacy topologies.
147    """
148    exec("import topologies.%s as Topo" % options.topology)
149    topology = eval("Topo.%s(controllers)" % options.topology)
150    return topology
151
152def create_system(options, full_system, system, piobus = None, dma_ports = [],
153                  bootmem=None):
154
155    system.ruby = RubySystem()
156    ruby = system.ruby
157
158    # Generate pseudo filesystem
159    FileSystemConfig.config_filesystem(system, options)
160
161    # Create the network object
162    (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
163        Network.create_network(options, ruby)
164    ruby.network = network
165
166    protocol = buildEnv['PROTOCOL']
167    exec("from . import %s" % protocol)
168    try:
169        (cpu_sequencers, dir_cntrls, topology) = \
170             eval("%s.create_system(options, full_system, system, dma_ports,\
171                                    bootmem, ruby)"
172                  % protocol)
173    except:
174        print("Error: could not create sytem for ruby protocol %s" % protocol)
175        raise
176
177    # Create the network topology
178    topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
179            RouterClass)
180
181    # Register the topology elements with faux filesystem (SE mode only)
182    if not full_system:
183        topology.registerTopology(options)
184
185
186    # Initialize network based on topology
187    Network.init_network(options, network, InterfaceClass)
188
189    # Create a port proxy for connecting the system port. This is
190    # independent of the protocol and kept in the protocol-agnostic
191    # part (i.e. here).
192    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
193    if piobus is not None:
194        sys_port_proxy.pio_master_port = piobus.slave
195
196    # Give the system port proxy a SimObject parent without creating a
197    # full-fledged controller
198    system.sys_port_proxy = sys_port_proxy
199
200    # Connect the system port for loading of binaries etc
201    system.system_port = system.sys_port_proxy.slave
202
203    setup_memory_controllers(system, ruby, dir_cntrls, options)
204
205    # Connect the cpu sequencers and the piobus
206    if piobus != None:
207        for cpu_seq in cpu_sequencers:
208            cpu_seq.pio_master_port = piobus.slave
209            cpu_seq.mem_master_port = piobus.slave
210
211            if buildEnv['TARGET_ISA'] == "x86":
212                cpu_seq.pio_slave_port = piobus.master
213
214    ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
215    ruby._cpu_ports = cpu_sequencers
216    ruby.num_of_sequencers = len(cpu_sequencers)
217
218    # Create a backing copy of physical memory in case required
219    if options.access_backing_store:
220        ruby.access_backing_store = True
221        ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
222                                     in_addr_map=False)
223
224def create_directories(options, bootmem, ruby_system, system):
225    dir_cntrl_nodes = []
226    for i in range(options.num_dirs):
227        dir_cntrl = Directory_Controller()
228        dir_cntrl.version = i
229        dir_cntrl.directory = RubyDirectoryMemory()
230        dir_cntrl.ruby_system = ruby_system
231
232        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
233        dir_cntrl_nodes.append(dir_cntrl)
234
235    if bootmem is not None:
236        rom_dir_cntrl = Directory_Controller()
237        rom_dir_cntrl.directory = RubyDirectoryMemory()
238        rom_dir_cntrl.ruby_system = ruby_system
239        rom_dir_cntrl.version = i + 1
240        rom_dir_cntrl.memory = bootmem.port
241        rom_dir_cntrl.addr_ranges = bootmem.range
242        return (dir_cntrl_nodes, rom_dir_cntrl)
243
244    return (dir_cntrl_nodes, None)
245
246def send_evicts(options):
247    # currently, 2 scenarios warrant forwarding evictions to the CPU:
248    # 1. The O3 model must keep the LSQ coherent with the caches
249    # 2. The x86 mwait instruction is built on top of coherence invalidations
250    # 3. The local exclusive monitor in ARM systems
251    if options.cpu_type == "DerivO3CPU" or \
252       buildEnv['TARGET_ISA'] in ('x86', 'arm'):
253        return True
254    return False
255