Ruby.py revision 13774:a1be2a0c55f2 
1# Copyright (c) 2012, 2017-2018 ARM Limited
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# Copyright (c) 2009 Advanced Micro Devices, Inc.
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39#
40# Authors: Brad Beckmann
41
42from __future__ import print_function
43
44import math
45import m5
46from m5.objects import *
47from m5.defines import buildEnv
48from m5.util import addToPath, fatal
49
50addToPath('../')
51
52from common import MemConfig
53
54from topologies import *
55from network import Network
56
57def define_options(parser):
58    # By default, ruby uses the simple timing cpu
59    parser.set_defaults(cpu_type="TimingSimpleCPU")
60
61    parser.add_option("--ruby-clock", action="store", type="string",
62                      default='2GHz',
63                      help="Clock for blocks running at Ruby system's speed")
64
65    parser.add_option("--access-backing-store", action="store_true", default=False,
66                      help="Should ruby maintain a second copy of memory")
67
68    # Options related to cache structure
69    parser.add_option("--ports", action="store", type="int", default=4,
70                      help="used of transitions per cycle which is a proxy \
71                            for the number of ports.")
72
73    # network options are in network/Network.py
74
75    # ruby mapping options
76    parser.add_option("--numa-high-bit", type="int", default=0,
77                      help="high order address bit to use for numa mapping. " \
78                           "0 = highest bit, not specified = lowest bit")
79
80    parser.add_option("--recycle-latency", type="int", default=10,
81                      help="Recycle latency for ruby controller input buffers")
82
83    protocol = buildEnv['PROTOCOL']
84    exec("from . import %s" % protocol)
85    eval("%s.define_options(parser)" % protocol)
86    Network.define_options(parser)
87
88def setup_memory_controllers(system, ruby, dir_cntrls, options):
89    ruby.block_size_bytes = options.cacheline_size
90    ruby.memory_size_bits = 48
91
92    index = 0
93    mem_ctrls = []
94    crossbars = []
95
96    if options.numa_high_bit:
97        dir_bits = int(math.log(options.num_dirs, 2))
98        intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1)
99    else:
100        # if the numa_bit is not specified, set the directory bits as the
101        # lowest bits above the block offset bits
102        intlv_size = options.cacheline_size
103
104    # Sets bits to be used for interleaving.  Creates memory controllers
105    # attached to a directory controller.  A separate controller is created
106    # for each address range as the abstract memory can handle only one
107    # contiguous address range as of now.
108    for dir_cntrl in dir_cntrls:
109        crossbar = None
110        if len(system.mem_ranges) > 1:
111            crossbar = IOXBar()
112            crossbars.append(crossbar)
113            dir_cntrl.memory = crossbar.slave
114
115        dir_ranges = []
116        for r in system.mem_ranges:
117            mem_ctrl = MemConfig.create_mem_ctrl(
118                MemConfig.get(options.mem_type), r, index, options.num_dirs,
119                int(math.log(options.num_dirs, 2)), intlv_size)
120
121            if options.access_backing_store:
122                mem_ctrl.kvm_map=False
123
124            mem_ctrls.append(mem_ctrl)
125            dir_ranges.append(mem_ctrl.range)
126
127            if crossbar != None:
128                mem_ctrl.port = crossbar.master
129            else:
130                mem_ctrl.port = dir_cntrl.memory
131
132        index += 1
133        dir_cntrl.addr_ranges = dir_ranges
134
135    system.mem_ctrls = mem_ctrls
136
137    if len(crossbars) > 0:
138        ruby.crossbars = crossbars
139
140
141def create_topology(controllers, options):
142    """ Called from create_system in configs/ruby/<protocol>.py
143        Must return an object which is a subclass of BaseTopology
144        found in configs/topologies/BaseTopology.py
145        This is a wrapper for the legacy topologies.
146    """
147    exec("import topologies.%s as Topo" % options.topology)
148    topology = eval("Topo.%s(controllers)" % options.topology)
149    return topology
150
151def create_system(options, full_system, system, piobus = None, dma_ports = [],
152                  bootmem=None):
153
154    system.ruby = RubySystem()
155    ruby = system.ruby
156
157    # Create the network object
158    (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
159        Network.create_network(options, ruby)
160    ruby.network = network
161
162    protocol = buildEnv['PROTOCOL']
163    exec("from . import %s" % protocol)
164    try:
165        (cpu_sequencers, dir_cntrls, topology) = \
166             eval("%s.create_system(options, full_system, system, dma_ports,\
167                                    bootmem, ruby)"
168                  % protocol)
169    except:
170        print("Error: could not create sytem for ruby protocol %s" % protocol)
171        raise
172
173    # Create the network topology
174    topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
175            RouterClass)
176
177    # Initialize network based on topology
178    Network.init_network(options, network, InterfaceClass)
179
180    # Create a port proxy for connecting the system port. This is
181    # independent of the protocol and kept in the protocol-agnostic
182    # part (i.e. here).
183    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
184    if piobus is not None:
185        sys_port_proxy.pio_master_port = piobus.slave
186
187    # Give the system port proxy a SimObject parent without creating a
188    # full-fledged controller
189    system.sys_port_proxy = sys_port_proxy
190
191    # Connect the system port for loading of binaries etc
192    system.system_port = system.sys_port_proxy.slave
193
194    setup_memory_controllers(system, ruby, dir_cntrls, options)
195
196    # Connect the cpu sequencers and the piobus
197    if piobus != None:
198        for cpu_seq in cpu_sequencers:
199            cpu_seq.pio_master_port = piobus.slave
200            cpu_seq.mem_master_port = piobus.slave
201
202            if buildEnv['TARGET_ISA'] == "x86":
203                cpu_seq.pio_slave_port = piobus.master
204
205    ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
206    ruby._cpu_ports = cpu_sequencers
207    ruby.num_of_sequencers = len(cpu_sequencers)
208
209    # Create a backing copy of physical memory in case required
210    if options.access_backing_store:
211        ruby.access_backing_store = True
212        ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
213                                     in_addr_map=False)
214
215def create_directories(options, bootmem, ruby_system, system):
216    dir_cntrl_nodes = []
217    for i in range(options.num_dirs):
218        dir_cntrl = Directory_Controller()
219        dir_cntrl.version = i
220        dir_cntrl.directory = RubyDirectoryMemory()
221        dir_cntrl.ruby_system = ruby_system
222
223        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
224        dir_cntrl_nodes.append(dir_cntrl)
225
226    if bootmem is not None:
227        rom_dir_cntrl = Directory_Controller()
228        rom_dir_cntrl.directory = RubyDirectoryMemory()
229        rom_dir_cntrl.ruby_system = ruby_system
230        rom_dir_cntrl.version = i + 1
231        rom_dir_cntrl.memory = bootmem.port
232        rom_dir_cntrl.addr_ranges = bootmem.range
233        return (dir_cntrl_nodes, rom_dir_cntrl)
234
235    return (dir_cntrl_nodes, None)
236
237def send_evicts(options):
238    # currently, 2 scenarios warrant forwarding evictions to the CPU:
239    # 1. The O3 model must keep the LSQ coherent with the caches
240    # 2. The x86 mwait instruction is built on top of coherence invalidations
241    # 3. The local exclusive monitor in ARM systems
242    if options.cpu_type == "DerivO3CPU" or \
243       buildEnv['TARGET_ISA'] in ('x86', 'arm'):
244        return True
245    return False
246