Ruby.py revision 12976:125099a94768 
1# Copyright (c) 2012, 2017-2018 ARM Limited
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# Copyright (c) 2009 Advanced Micro Devices, Inc.
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39#
40# Authors: Brad Beckmann
41
42from __future__ import print_function
43
44import math
45import m5
46from m5.objects import *
47from m5.defines import buildEnv
48from m5.util import addToPath, fatal
49
50from common import MemConfig
51
52from topologies import *
53from network import Network
54
55def define_options(parser):
56    # By default, ruby uses the simple timing cpu
57    parser.set_defaults(cpu_type="TimingSimpleCPU")
58
59    parser.add_option("--ruby-clock", action="store", type="string",
60                      default='2GHz',
61                      help="Clock for blocks running at Ruby system's speed")
62
63    parser.add_option("--access-backing-store", action="store_true", default=False,
64                      help="Should ruby maintain a second copy of memory")
65
66    # Options related to cache structure
67    parser.add_option("--ports", action="store", type="int", default=4,
68                      help="used of transitions per cycle which is a proxy \
69                            for the number of ports.")
70
71    # network options are in network/Network.py
72
73    # ruby mapping options
74    parser.add_option("--numa-high-bit", type="int", default=0,
75                      help="high order address bit to use for numa mapping. " \
76                           "0 = highest bit, not specified = lowest bit")
77
78    parser.add_option("--recycle-latency", type="int", default=10,
79                      help="Recycle latency for ruby controller input buffers")
80
81    protocol = buildEnv['PROTOCOL']
82    exec "import %s" % protocol
83    eval("%s.define_options(parser)" % protocol)
84    Network.define_options(parser)
85
86def setup_memory_controllers(system, ruby, dir_cntrls, options):
87    ruby.block_size_bytes = options.cacheline_size
88    ruby.memory_size_bits = 48
89
90    index = 0
91    mem_ctrls = []
92    crossbars = []
93
94    if options.numa_high_bit:
95        dir_bits = int(math.log(options.num_dirs, 2))
96        intlv_size = 2 ** (options.numa_high_bit - dir_bits + 1)
97    else:
98        # if the numa_bit is not specified, set the directory bits as the
99        # lowest bits above the block offset bits
100        intlv_size = options.cacheline_size
101
102    # Sets bits to be used for interleaving.  Creates memory controllers
103    # attached to a directory controller.  A separate controller is created
104    # for each address range as the abstract memory can handle only one
105    # contiguous address range as of now.
106    for dir_cntrl in dir_cntrls:
107        crossbar = None
108        if len(system.mem_ranges) > 1:
109            crossbar = IOXBar()
110            crossbars.append(crossbar)
111            dir_cntrl.memory = crossbar.slave
112
113        dir_ranges = []
114        for r in system.mem_ranges:
115            mem_ctrl = MemConfig.create_mem_ctrl(
116                MemConfig.get(options.mem_type), r, index, options.num_dirs,
117                int(math.log(options.num_dirs, 2)), intlv_size)
118
119            if options.access_backing_store:
120                mem_ctrl.kvm_map=False
121
122            mem_ctrls.append(mem_ctrl)
123            dir_ranges.append(mem_ctrl.range)
124
125            if crossbar != None:
126                mem_ctrl.port = crossbar.master
127            else:
128                mem_ctrl.port = dir_cntrl.memory
129
130        index += 1
131        dir_cntrl.addr_ranges = dir_ranges
132
133    system.mem_ctrls = mem_ctrls
134
135    if len(crossbars) > 0:
136        ruby.crossbars = crossbars
137
138
139def create_topology(controllers, options):
140    """ Called from create_system in configs/ruby/<protocol>.py
141        Must return an object which is a subclass of BaseTopology
142        found in configs/topologies/BaseTopology.py
143        This is a wrapper for the legacy topologies.
144    """
145    exec "import topologies.%s as Topo" % options.topology
146    topology = eval("Topo.%s(controllers)" % options.topology)
147    return topology
148
149def create_system(options, full_system, system, piobus = None, dma_ports = [],
150                  bootmem=None):
151
152    system.ruby = RubySystem()
153    ruby = system.ruby
154
155    # Create the network object
156    (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
157        Network.create_network(options, ruby)
158    ruby.network = network
159
160    protocol = buildEnv['PROTOCOL']
161    exec "import %s" % protocol
162    try:
163        (cpu_sequencers, dir_cntrls, topology) = \
164             eval("%s.create_system(options, full_system, system, dma_ports,\
165                                    bootmem, ruby)"
166                  % protocol)
167    except:
168        print("Error: could not create sytem for ruby protocol %s" % protocol)
169        raise
170
171    # Create the network topology
172    topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
173            RouterClass)
174
175    # Initialize network based on topology
176    Network.init_network(options, network, InterfaceClass)
177
178    # Create a port proxy for connecting the system port. This is
179    # independent of the protocol and kept in the protocol-agnostic
180    # part (i.e. here).
181    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
182    if piobus is not None:
183        sys_port_proxy.pio_master_port = piobus.slave
184
185    # Give the system port proxy a SimObject parent without creating a
186    # full-fledged controller
187    system.sys_port_proxy = sys_port_proxy
188
189    # Connect the system port for loading of binaries etc
190    system.system_port = system.sys_port_proxy.slave
191
192    setup_memory_controllers(system, ruby, dir_cntrls, options)
193
194    # Connect the cpu sequencers and the piobus
195    if piobus != None:
196        for cpu_seq in cpu_sequencers:
197            cpu_seq.pio_master_port = piobus.slave
198            cpu_seq.mem_master_port = piobus.slave
199
200            if buildEnv['TARGET_ISA'] == "x86":
201                cpu_seq.pio_slave_port = piobus.master
202
203    ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
204    ruby._cpu_ports = cpu_sequencers
205    ruby.num_of_sequencers = len(cpu_sequencers)
206
207    # Create a backing copy of physical memory in case required
208    if options.access_backing_store:
209        ruby.access_backing_store = True
210        ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
211                                     in_addr_map=False)
212
213def create_directories(options, bootmem, ruby_system, system):
214    dir_cntrl_nodes = []
215    for i in xrange(options.num_dirs):
216        dir_cntrl = Directory_Controller()
217        dir_cntrl.version = i
218        dir_cntrl.directory = RubyDirectoryMemory()
219        dir_cntrl.ruby_system = ruby_system
220
221        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
222        dir_cntrl_nodes.append(dir_cntrl)
223
224    if bootmem is not None:
225        rom_dir_cntrl = Directory_Controller()
226        rom_dir_cntrl.directory = RubyDirectoryMemory()
227        rom_dir_cntrl.ruby_system = ruby_system
228        rom_dir_cntrl.version = i + 1
229        rom_dir_cntrl.memory = bootmem.port
230        rom_dir_cntrl.addr_ranges = bootmem.range
231        return (dir_cntrl_nodes, rom_dir_cntrl)
232
233    return (dir_cntrl_nodes, None)
234
235def send_evicts(options):
236    # currently, 2 scenarios warrant forwarding evictions to the CPU:
237    # 1. The O3 model must keep the LSQ coherent with the caches
238    # 2. The x86 mwait instruction is built on top of coherence invalidations
239    # 3. The local exclusive monitor in ARM systems
240    if options.cpu_type == "DerivO3CPU" or \
241       buildEnv['TARGET_ISA'] in ('x86', 'arm'):
242        return True
243    return False
244