Ruby.py revision 12066:a4fd03c9ca5a
1955SN/A# Copyright (c) 2012, 2017 ARM Limited
2955SN/A# All rights reserved.
311408Sandreas.sandberg@arm.com#
49812Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall
59812Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual
69812Sandreas.hansson@arm.com# property including but not limited to intellectual property relating
79812Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software
89812Sandreas.hansson@arm.com# licensed hereunder.  You may use the software subject to the license
99812Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated
109812Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software,
119812Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form.
129812Sandreas.hansson@arm.com#
139812Sandreas.hansson@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
149812Sandreas.hansson@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc.
157816Ssteve.reinhardt@amd.com# All rights reserved.
165871Snate@binkert.org#
171762SN/A# Redistribution and use in source and binary forms, with or without
18955SN/A# modification, are permitted provided that the following conditions are
19955SN/A# met: redistributions of source code must retain the above copyright
20955SN/A# notice, this list of conditions and the following disclaimer;
21955SN/A# redistributions in binary form must reproduce the above copyright
22955SN/A# notice, this list of conditions and the following disclaimer in the
23955SN/A# documentation and/or other materials provided with the distribution;
24955SN/A# neither the name of the copyright holders nor the names of its
25955SN/A# contributors may be used to endorse or promote products derived from
26955SN/A# this software without specific prior written permission.
27955SN/A#
28955SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30955SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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34955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38955SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39955SN/A#
40955SN/A# Authors: Brad Beckmann
41955SN/A
422665Ssaidi@eecs.umich.eduimport math
432665Ssaidi@eecs.umich.eduimport m5
445863Snate@binkert.orgfrom m5.objects import *
45955SN/Afrom m5.defines import buildEnv
46955SN/Afrom m5.util import addToPath, fatal
47955SN/A
48955SN/Afrom common import MemConfig
49955SN/A
508878Ssteve.reinhardt@amd.comfrom topologies import *
512632Sstever@eecs.umich.edufrom network import Network
528878Ssteve.reinhardt@amd.com
532632Sstever@eecs.umich.edudef define_options(parser):
54955SN/A    # By default, ruby uses the simple timing cpu
558878Ssteve.reinhardt@amd.com    parser.set_defaults(cpu_type="TimingSimpleCPU")
562632Sstever@eecs.umich.edu
572761Sstever@eecs.umich.edu    parser.add_option("--ruby-clock", action="store", type="string",
582632Sstever@eecs.umich.edu                      default='2GHz',
592632Sstever@eecs.umich.edu                      help="Clock for blocks running at Ruby system's speed")
602632Sstever@eecs.umich.edu
612761Sstever@eecs.umich.edu    parser.add_option("--access-backing-store", action="store_true", default=False,
622761Sstever@eecs.umich.edu                      help="Should ruby maintain a second copy of memory")
632761Sstever@eecs.umich.edu
648878Ssteve.reinhardt@amd.com    # Options related to cache structure
658878Ssteve.reinhardt@amd.com    parser.add_option("--ports", action="store", type="int", default=4,
662761Sstever@eecs.umich.edu                      help="used of transitions per cycle which is a proxy \
672761Sstever@eecs.umich.edu                            for the number of ports.")
682761Sstever@eecs.umich.edu
692761Sstever@eecs.umich.edu    # network options are in network/Network.py
702761Sstever@eecs.umich.edu
718878Ssteve.reinhardt@amd.com    # ruby mapping options
728878Ssteve.reinhardt@amd.com    parser.add_option("--numa-high-bit", type="int", default=0,
732632Sstever@eecs.umich.edu                      help="high order address bit to use for numa mapping. " \
742632Sstever@eecs.umich.edu                           "0 = highest bit, not specified = lowest bit")
758878Ssteve.reinhardt@amd.com
768878Ssteve.reinhardt@amd.com    parser.add_option("--recycle-latency", type="int", default=10,
772632Sstever@eecs.umich.edu                      help="Recycle latency for ruby controller input buffers")
78955SN/A
79955SN/A    protocol = buildEnv['PROTOCOL']
80955SN/A    exec "import %s" % protocol
815863Snate@binkert.org    eval("%s.define_options(parser)" % protocol)
825863Snate@binkert.org    Network.define_options(parser)
835863Snate@binkert.org
845863Snate@binkert.orgdef setup_memory_controllers(system, ruby, dir_cntrls, options):
855863Snate@binkert.org    ruby.block_size_bytes = options.cacheline_size
865863Snate@binkert.org    ruby.memory_size_bits = 48
875863Snate@binkert.org
885863Snate@binkert.org    index = 0
895863Snate@binkert.org    mem_ctrls = []
905863Snate@binkert.org    crossbars = []
915863Snate@binkert.org
928878Ssteve.reinhardt@amd.com    # Sets bits to be used for interleaving.  Creates memory controllers
935863Snate@binkert.org    # attached to a directory controller.  A separate controller is created
945863Snate@binkert.org    # for each address range as the abstract memory can handle only one
955863Snate@binkert.org    # contiguous address range as of now.
969812Sandreas.hansson@arm.com    for dir_cntrl in dir_cntrls:
979812Sandreas.hansson@arm.com        crossbar = None
985863Snate@binkert.org        if len(system.mem_ranges) > 1:
999812Sandreas.hansson@arm.com            crossbar = IOXBar()
1005863Snate@binkert.org            crossbars.append(crossbar)
1015863Snate@binkert.org            dir_cntrl.memory = crossbar.slave
1025863Snate@binkert.org
1039812Sandreas.hansson@arm.com        for r in system.mem_ranges:
1049812Sandreas.hansson@arm.com            mem_ctrl = MemConfig.create_mem_ctrl(
1055863Snate@binkert.org                MemConfig.get(options.mem_type), r, index, options.num_dirs,
1065863Snate@binkert.org                int(math.log(options.num_dirs, 2)), options.cacheline_size)
1078878Ssteve.reinhardt@amd.com
1085863Snate@binkert.org            if options.access_backing_store:
1095863Snate@binkert.org                mem_ctrl.kvm_map=False
1105863Snate@binkert.org
1116654Snate@binkert.org            mem_ctrls.append(mem_ctrl)
11210196SCurtis.Dunham@arm.com
113955SN/A            if crossbar != None:
1145396Ssaidi@eecs.umich.edu                mem_ctrl.port = crossbar.master
11511401Sandreas.sandberg@arm.com            else:
1165863Snate@binkert.org                mem_ctrl.port = dir_cntrl.memory
1175863Snate@binkert.org
1184202Sbinkertn@umich.edu        index += 1
1195863Snate@binkert.org
1205863Snate@binkert.org    system.mem_ctrls = mem_ctrls
1215863Snate@binkert.org
1225863Snate@binkert.org    if len(crossbars) > 0:
123955SN/A        ruby.crossbars = crossbars
1246654Snate@binkert.org
1255273Sstever@gmail.com
1265871Snate@binkert.orgdef create_topology(controllers, options):
1275273Sstever@gmail.com    """ Called from create_system in configs/ruby/<protocol>.py
1286655Snate@binkert.org        Must return an object which is a subclass of BaseTopology
1298878Ssteve.reinhardt@amd.com        found in configs/topologies/BaseTopology.py
1306655Snate@binkert.org        This is a wrapper for the legacy topologies.
1316655Snate@binkert.org    """
1329219Spower.jg@gmail.com    exec "import topologies.%s as Topo" % options.topology
1336655Snate@binkert.org    topology = eval("Topo.%s(controllers)" % options.topology)
1345871Snate@binkert.org    return topology
1356654Snate@binkert.org
1368947Sandreas.hansson@arm.comdef create_system(options, full_system, system, piobus = None, dma_ports = []):
1375396Ssaidi@eecs.umich.edu
1388120Sgblack@eecs.umich.edu    system.ruby = RubySystem()
1398120Sgblack@eecs.umich.edu    ruby = system.ruby
1408120Sgblack@eecs.umich.edu
1418120Sgblack@eecs.umich.edu    # Create the network object
1428120Sgblack@eecs.umich.edu    (network, IntLinkClass, ExtLinkClass, RouterClass, InterfaceClass) = \
1438120Sgblack@eecs.umich.edu        Network.create_network(options, ruby)
1448120Sgblack@eecs.umich.edu    ruby.network = network
1458120Sgblack@eecs.umich.edu
1468879Ssteve.reinhardt@amd.com    protocol = buildEnv['PROTOCOL']
1478879Ssteve.reinhardt@amd.com    exec "import %s" % protocol
1488879Ssteve.reinhardt@amd.com    try:
1498879Ssteve.reinhardt@amd.com        (cpu_sequencers, dir_cntrls, topology) = \
1508879Ssteve.reinhardt@amd.com             eval("%s.create_system(options, full_system, system, dma_ports,\
1518879Ssteve.reinhardt@amd.com                                    ruby)"
1528879Ssteve.reinhardt@amd.com                  % protocol)
1538879Ssteve.reinhardt@amd.com    except:
1548879Ssteve.reinhardt@amd.com        print "Error: could not create sytem for ruby protocol %s" % protocol
1558879Ssteve.reinhardt@amd.com        raise
1568879Ssteve.reinhardt@amd.com
1578879Ssteve.reinhardt@amd.com    # Create the network topology
1588879Ssteve.reinhardt@amd.com    topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
1598120Sgblack@eecs.umich.edu            RouterClass)
1608120Sgblack@eecs.umich.edu
1618120Sgblack@eecs.umich.edu    # Initialize network based on topology
1628120Sgblack@eecs.umich.edu    Network.init_network(options, network, InterfaceClass)
1638120Sgblack@eecs.umich.edu
1648120Sgblack@eecs.umich.edu    # Create a port proxy for connecting the system port. This is
1658120Sgblack@eecs.umich.edu    # independent of the protocol and kept in the protocol-agnostic
1668120Sgblack@eecs.umich.edu    # part (i.e. here).
1678120Sgblack@eecs.umich.edu    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
1688120Sgblack@eecs.umich.edu    if piobus is not None:
1698120Sgblack@eecs.umich.edu        sys_port_proxy.pio_master_port = piobus.slave
1708120Sgblack@eecs.umich.edu
1718120Sgblack@eecs.umich.edu    # Give the system port proxy a SimObject parent without creating a
1728120Sgblack@eecs.umich.edu    # full-fledged controller
1738879Ssteve.reinhardt@amd.com    system.sys_port_proxy = sys_port_proxy
1748879Ssteve.reinhardt@amd.com
1758879Ssteve.reinhardt@amd.com    # Connect the system port for loading of binaries etc
1768879Ssteve.reinhardt@amd.com    system.system_port = system.sys_port_proxy.slave
17710458Sandreas.hansson@arm.com
17810458Sandreas.hansson@arm.com    setup_memory_controllers(system, ruby, dir_cntrls, options)
17910458Sandreas.hansson@arm.com
1808879Ssteve.reinhardt@amd.com    # Connect the cpu sequencers and the piobus
1818879Ssteve.reinhardt@amd.com    if piobus != None:
1828879Ssteve.reinhardt@amd.com        for cpu_seq in cpu_sequencers:
1838879Ssteve.reinhardt@amd.com            cpu_seq.pio_master_port = piobus.slave
1849227Sandreas.hansson@arm.com            cpu_seq.mem_master_port = piobus.slave
1859227Sandreas.hansson@arm.com
1868879Ssteve.reinhardt@amd.com            if buildEnv['TARGET_ISA'] == "x86":
1878879Ssteve.reinhardt@amd.com                cpu_seq.pio_slave_port = piobus.master
1888879Ssteve.reinhardt@amd.com
1898879Ssteve.reinhardt@amd.com    ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
19010453SAndrew.Bardsley@arm.com    ruby._cpu_ports = cpu_sequencers
19110453SAndrew.Bardsley@arm.com    ruby.num_of_sequencers = len(cpu_sequencers)
19210453SAndrew.Bardsley@arm.com
19310456SCurtis.Dunham@arm.com    # Create a backing copy of physical memory in case required
19410456SCurtis.Dunham@arm.com    if options.access_backing_store:
19510456SCurtis.Dunham@arm.com        ruby.access_backing_store = True
19610457Sandreas.hansson@arm.com        ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
19710457Sandreas.hansson@arm.com                                     in_addr_map=False)
19811342Sandreas.hansson@arm.com
19911342Sandreas.hansson@arm.comdef create_directories(options, mem_ranges, ruby_system):
2008120Sgblack@eecs.umich.edu    dir_cntrl_nodes = []
2018947Sandreas.hansson@arm.com    if options.numa_high_bit:
2027816Ssteve.reinhardt@amd.com        numa_bit = options.numa_high_bit
2035871Snate@binkert.org    else:
2045871Snate@binkert.org        # if the numa_bit is not specified, set the directory bits as the
2056121Snate@binkert.org        # lowest bits above the block offset bits, and the numa_bit as the
2065871Snate@binkert.org        # highest of those directory bits
2075871Snate@binkert.org        dir_bits = int(math.log(options.num_dirs, 2))
2089926Sstan.czerniawski@arm.com        block_size_bits = int(math.log(options.cacheline_size, 2))
2099926Sstan.czerniawski@arm.com        numa_bit = block_size_bits + dir_bits - 1
2109119Sandreas.hansson@arm.com
21110068Sandreas.hansson@arm.com    for i in xrange(options.num_dirs):
21211989Sandreas.sandberg@arm.com        dir_ranges = []
213955SN/A        for r in mem_ranges:
2149416SAndreas.Sandberg@ARM.com            addr_range = m5.objects.AddrRange(r.start, size = r.size(),
21511342Sandreas.hansson@arm.com                                              intlvHighBit = numa_bit,
21611212Sjoseph.gross@amd.com                                              intlvBits = dir_bits,
21711212Sjoseph.gross@amd.com                                              intlvMatch = i)
21811212Sjoseph.gross@amd.com            dir_ranges.append(addr_range)
21911212Sjoseph.gross@amd.com
22011212Sjoseph.gross@amd.com        dir_cntrl = Directory_Controller()
2219416SAndreas.Sandberg@ARM.com        dir_cntrl.version = i
2229416SAndreas.Sandberg@ARM.com        dir_cntrl.directory = RubyDirectoryMemory()
2235871Snate@binkert.org        dir_cntrl.ruby_system = ruby_system
22410584Sandreas.hansson@arm.com        dir_cntrl.addr_ranges = dir_ranges
2259416SAndreas.Sandberg@ARM.com
2269416SAndreas.Sandberg@ARM.com        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
2275871Snate@binkert.org        dir_cntrl_nodes.append(dir_cntrl)
228955SN/A    return dir_cntrl_nodes
22910671Sandreas.hansson@arm.com
23010671Sandreas.hansson@arm.comdef send_evicts(options):
23110671Sandreas.hansson@arm.com    # currently, 2 scenarios warrant forwarding evictions to the CPU:
23210671Sandreas.hansson@arm.com    # 1. The O3 model must keep the LSQ coherent with the caches
2338881Smarc.orr@gmail.com    # 2. The x86 mwait instruction is built on top of coherence invalidations
2346121Snate@binkert.org    # 3. The local exclusive monitor in ARM systems
2356121Snate@binkert.org    if options.cpu_type == "DerivO3CPU" or \
2361533SN/A       buildEnv['TARGET_ISA'] in ('x86', 'arm'):
2379239Sandreas.hansson@arm.com        return True
2389239Sandreas.hansson@arm.com    return False
2399239Sandreas.hansson@arm.com