Ruby.py revision 10630:64618b7c57b2
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# Copyright (c) 2009 Advanced Micro Devices, Inc. 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Brad Beckmann 41 42import math 43import m5 44from m5.objects import * 45from m5.defines import buildEnv 46from m5.util import addToPath, fatal 47 48import MemConfig 49addToPath('../topologies') 50 51def define_options(parser): 52 # By default, ruby uses the simple timing cpu 53 parser.set_defaults(cpu_type="timing") 54 55 parser.add_option("--ruby-clock", action="store", type="string", 56 default='2GHz', 57 help="Clock for blocks running at Ruby system's speed") 58 59 parser.add_option("--access-backing-store", action="store_true", default=False, 60 help="Should ruby maintain a second copy of memory") 61 62 # Options related to cache structure 63 parser.add_option("--ports", action="store", type="int", default=4, 64 help="used of transitions per cycle which is a proxy \ 65 for the number of ports.") 66 67 # ruby network options 68 parser.add_option("--topology", type="string", default="Crossbar", 69 help="check src/mem/ruby/network/topologies for complete set") 70 parser.add_option("--mesh-rows", type="int", default=1, 71 help="the number of rows in the mesh topology") 72 parser.add_option("--garnet-network", type="choice", 73 choices=['fixed', 'flexible'], help="'fixed'|'flexible'") 74 parser.add_option("--network-fault-model", action="store_true", default=False, 75 help="enable network fault model: see src/mem/ruby/network/fault_model/") 76 77 # ruby mapping options 78 parser.add_option("--numa-high-bit", type="int", default=0, 79 help="high order address bit to use for numa mapping. " \ 80 "0 = highest bit, not specified = lowest bit") 81 82 parser.add_option("--recycle-latency", type="int", default=10, 83 help="Recycle latency for ruby controller input buffers") 84 85 parser.add_option("--random_seed", type="int", default=1234, 86 help="Used for seeding the random number generator") 87 88 protocol = buildEnv['PROTOCOL'] 89 exec "import %s" % protocol 90 eval("%s.define_options(parser)" % protocol) 91 92def setup_memory_controllers(system, ruby, dir_cntrls, options): 93 ruby.block_size_bytes = options.cacheline_size 94 ruby.memory_size_bits = 48 95 block_size_bits = int(math.log(options.cacheline_size, 2)) 96 97 if options.numa_high_bit: 98 numa_bit = options.numa_high_bit 99 else: 100 # if the numa_bit is not specified, set the directory bits as the 101 # lowest bits above the block offset bits, and the numa_bit as the 102 # highest of those directory bits 103 dir_bits = int(math.log(options.num_dirs, 2)) 104 numa_bit = block_size_bits + dir_bits - 1 105 106 index = 0 107 mem_ctrls = [] 108 crossbars = [] 109 110 # Sets bits to be used for interleaving. Creates memory controllers 111 # attached to a directory controller. A separate controller is created 112 # for each address range as the abstract memory can handle only one 113 # contiguous address range as of now. 114 for dir_cntrl in dir_cntrls: 115 dir_cntrl.directory.numa_high_bit = numa_bit 116 117 crossbar = None 118 if len(system.mem_ranges) > 1: 119 crossbar = NoncoherentXBar() 120 crossbars.append(crossbar) 121 dir_cntrl.memory = crossbar.slave 122 123 for r in system.mem_ranges: 124 mem_ctrl = MemConfig.create_mem_ctrl( 125 MemConfig.get(options.mem_type), r, index, options.num_dirs, 126 int(math.log(options.num_dirs, 2)), options.cacheline_size) 127 128 mem_ctrls.append(mem_ctrl) 129 130 if crossbar != None: 131 mem_ctrl.port = crossbar.master 132 else: 133 mem_ctrl.port = dir_cntrl.memory 134 135 index += 1 136 137 system.mem_ctrls = mem_ctrls 138 139 if len(crossbars) > 0: 140 ruby.crossbars = crossbars 141 142 143def create_topology(controllers, options): 144 """ Called from create_system in configs/ruby/<protocol>.py 145 Must return an object which is a subclass of BaseTopology 146 found in configs/topologies/BaseTopology.py 147 This is a wrapper for the legacy topologies. 148 """ 149 exec "import %s as Topo" % options.topology 150 topology = eval("Topo.%s(controllers)" % options.topology) 151 return topology 152 153def create_system(options, full_system, system, piobus = None, dma_ports = []): 154 155 system.ruby = RubySystem() 156 ruby = system.ruby 157 158 # Set the network classes based on the command line options 159 if options.garnet_network == "fixed": 160 NetworkClass = GarnetNetwork_d 161 IntLinkClass = GarnetIntLink_d 162 ExtLinkClass = GarnetExtLink_d 163 RouterClass = GarnetRouter_d 164 InterfaceClass = GarnetNetworkInterface_d 165 166 elif options.garnet_network == "flexible": 167 NetworkClass = GarnetNetwork 168 IntLinkClass = GarnetIntLink 169 ExtLinkClass = GarnetExtLink 170 RouterClass = GarnetRouter 171 InterfaceClass = GarnetNetworkInterface 172 173 else: 174 NetworkClass = SimpleNetwork 175 IntLinkClass = SimpleIntLink 176 ExtLinkClass = SimpleExtLink 177 RouterClass = Switch 178 InterfaceClass = None 179 180 # Instantiate the network object so that the controllers can connect to it. 181 network = NetworkClass(ruby_system = ruby, topology = options.topology, 182 routers = [], ext_links = [], int_links = [], netifs = []) 183 ruby.network = network 184 185 protocol = buildEnv['PROTOCOL'] 186 exec "import %s" % protocol 187 try: 188 (cpu_sequencers, dir_cntrls, topology) = \ 189 eval("%s.create_system(options, full_system, system, dma_ports,\ 190 ruby)" 191 % protocol) 192 except: 193 print "Error: could not create sytem for ruby protocol %s" % protocol 194 raise 195 196 # Create a port proxy for connecting the system port. This is 197 # independent of the protocol and kept in the protocol-agnostic 198 # part (i.e. here). 199 sys_port_proxy = RubyPortProxy(ruby_system = ruby) 200 201 # Give the system port proxy a SimObject parent without creating a 202 # full-fledged controller 203 system.sys_port_proxy = sys_port_proxy 204 205 # Connect the system port for loading of binaries etc 206 system.system_port = system.sys_port_proxy.slave 207 208 # Create the network topology 209 topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, 210 RouterClass) 211 212 if InterfaceClass != None: 213 netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)] 214 network.netifs = netifs 215 216 if options.network_fault_model: 217 assert(options.garnet_network == "fixed") 218 network.enable_fault_model = True 219 network.fault_model = FaultModel() 220 221 setup_memory_controllers(system, ruby, dir_cntrls, options) 222 223 # Connect the cpu sequencers and the piobus 224 if piobus != None: 225 for cpu_seq in cpu_sequencers: 226 cpu_seq.pio_master_port = piobus.slave 227 cpu_seq.mem_master_port = piobus.slave 228 229 if buildEnv['TARGET_ISA'] == "x86": 230 cpu_seq.pio_slave_port = piobus.master 231 232 ruby._cpu_ports = cpu_sequencers 233 ruby.num_of_sequencers = len(cpu_sequencers) 234 ruby.random_seed = options.random_seed 235 236 # Create a backing copy of physical memory in case required 237 if options.access_backing_store: 238 ruby.phys_mem = SimpleMemory(range=AddrRange(options.mem_size), 239 in_addr_map=False) 240 241def send_evicts(options): 242 # currently, 2 scenarios warrant forwarding evictions to the CPU: 243 # 1. The O3 model must keep the LSQ coherent with the caches 244 # 2. The x86 mwait instruction is built on top of coherence invalidations 245 if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86': 246 return True 247 return False 248