Ruby.py revision 10550:f9fb64a72259 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# Copyright (c) 2009 Advanced Micro Devices, Inc.
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Brad Beckmann
41
42import importlib
43import math
44import m5
45from m5.objects import *
46from m5.defines import buildEnv
47from m5.util import addToPath, fatal
48
49import MemConfig
50addToPath('../topologies')
51
52def define_options(parser):
53    # By default, ruby uses the simple timing cpu
54    parser.set_defaults(cpu_type="timing")
55
56    parser.add_option("--ruby-clock", action="store", type="string",
57                      default='2GHz',
58                      help="Clock for blocks running at Ruby system's speed")
59
60    parser.add_option("--access-backing-store", action="store_true", default=False,
61                      help="Should ruby maintain a second copy of memory")
62
63    # Options related to cache structure
64    parser.add_option("--ports", action="store", type="int", default=4,
65                      help="used of transitions per cycle which is a proxy \
66                            for the number of ports.")
67
68    # ruby network options
69    parser.add_option("--topology", type="string", default="Crossbar",
70                 help="check src/mem/ruby/network/topologies for complete set")
71    parser.add_option("--mesh-rows", type="int", default=1,
72                      help="the number of rows in the mesh topology")
73    parser.add_option("--garnet-network", type="choice",
74                      choices=['fixed', 'flexible'], help="'fixed'|'flexible'")
75    parser.add_option("--network-fault-model", action="store_true", default=False,
76                      help="enable network fault model: see src/mem/ruby/network/fault_model/")
77
78    # ruby mapping options
79    parser.add_option("--numa-high-bit", type="int", default=0,
80                      help="high order address bit to use for numa mapping. " \
81                           "0 = highest bit, not specified = lowest bit")
82
83    parser.add_option("--recycle-latency", type="int", default=10,
84                      help="Recycle latency for ruby controller input buffers")
85
86    parser.add_option("--random_seed", type="int", default=1234,
87                      help="Used for seeding the random number generator")
88
89    protocol = buildEnv['PROTOCOL']
90    exec "import %s" % protocol
91    eval("%s.define_options(parser)" % protocol)
92
93def setup_memory_controllers(system, ruby, dir_cntrls, options):
94    ruby.block_size_bytes = options.cacheline_size
95    ruby.memory_size_bits = 48
96    block_size_bits = int(math.log(options.cacheline_size, 2))
97
98    if options.numa_high_bit:
99        numa_bit = options.numa_high_bit
100    else:
101        # if the numa_bit is not specified, set the directory bits as the
102        # lowest bits above the block offset bits, and the numa_bit as the
103        # highest of those directory bits
104        dir_bits = int(math.log(options.num_dirs, 2))
105        numa_bit = block_size_bits + dir_bits - 1
106
107    index = 0
108    mem_ctrls = []
109    crossbars = []
110
111    # Sets bits to be used for interleaving.  Creates memory controllers
112    # attached to a directory controller.  A separate controller is created
113    # for each address range as the abstract memory can handle only one
114    # contiguous address range as of now.
115    for dir_cntrl in dir_cntrls:
116        dir_cntrl.directory.numa_high_bit = numa_bit
117
118        crossbar = None
119        if len(system.mem_ranges) > 1:
120            crossbar = NoncoherentXBar()
121            crossbars.append(crossbar)
122            dir_cntrl.memory = crossbar.slave
123
124        for r in system.mem_ranges:
125            mem_ctrl = MemConfig.create_mem_ctrl(
126                MemConfig.get(options.mem_type), r, index, options.num_dirs,
127                int(math.log(options.num_dirs, 2)), options.cacheline_size)
128
129            mem_ctrls.append(mem_ctrl)
130
131            if crossbar != None:
132                mem_ctrl.port = crossbar.master
133            else:
134                mem_ctrl.port = dir_cntrl.memory
135
136        index += 1
137
138    system.mem_ctrls = mem_ctrls
139
140    if len(crossbars) > 0:
141        ruby.crossbars = crossbars
142
143
144def create_topology(controllers, options):
145    """ Called from create_system in configs/ruby/<protocol>.py
146        Must return an object which is a subclass of BaseTopology
147        found in configs/topologies/BaseTopology.py
148        This is a wrapper for the legacy topologies.
149    """
150    exec "import %s as Topo" % options.topology
151    topology = eval("Topo.%s(controllers)" % options.topology)
152    return topology
153
154def create_system(options, full_system, system, piobus = None, dma_ports = []):
155
156    system.ruby = RubySystem()
157    ruby = system.ruby
158
159    # Set the network classes based on the command line options
160    if options.garnet_network == "fixed":
161        NetworkClass = GarnetNetwork_d
162        IntLinkClass = GarnetIntLink_d
163        ExtLinkClass = GarnetExtLink_d
164        RouterClass = GarnetRouter_d
165        InterfaceClass = GarnetNetworkInterface_d
166
167    elif options.garnet_network == "flexible":
168        NetworkClass = GarnetNetwork
169        IntLinkClass = GarnetIntLink
170        ExtLinkClass = GarnetExtLink
171        RouterClass = GarnetRouter
172        InterfaceClass = GarnetNetworkInterface
173
174    else:
175        NetworkClass = SimpleNetwork
176        IntLinkClass = SimpleIntLink
177        ExtLinkClass = SimpleExtLink
178        RouterClass = Switch
179        InterfaceClass = None
180
181    # Instantiate the network object so that the controllers can connect to it.
182    network = NetworkClass(ruby_system = ruby, topology = options.topology,
183            routers = [], ext_links = [], int_links = [], netifs = [])
184    ruby.network = network
185
186    protocol_name = buildEnv['PROTOCOL']
187    protocol = importlib.import_module(protocol_name)
188    try:
189        (cpu_sequencers, dir_cntrls, topology) = \
190             protocol.create_system(options, full_system, system, dma_ports,
191                                    ruby)
192    except:
193        print "Error: could not create sytem for ruby protocol %s" % \
194            protocol_name
195        raise
196
197    # Create a port proxy for connecting the system port. This is
198    # independent of the protocol and kept in the protocol-agnostic
199    # part (i.e. here).
200    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
201
202    # Give the system port proxy a SimObject parent without creating a
203    # full-fledged controller
204    system.sys_port_proxy = sys_port_proxy
205
206    # Connect the system port for loading of binaries etc
207    system.system_port = system.sys_port_proxy.slave
208
209    # Create the network topology
210    topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
211            RouterClass)
212
213    if InterfaceClass != None:
214        netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)]
215        network.netifs = netifs
216
217    if options.network_fault_model:
218        assert(options.garnet_network == "fixed")
219        network.enable_fault_model = True
220        network.fault_model = FaultModel()
221
222    setup_memory_controllers(system, ruby, dir_cntrls, options)
223
224    # Connect the cpu sequencers and the piobus
225    if piobus != None:
226        for cpu_seq in cpu_sequencers:
227            cpu_seq.pio_master_port = piobus.slave
228            cpu_seq.mem_master_port = piobus.slave
229
230            if buildEnv['TARGET_ISA'] == "x86":
231                cpu_seq.pio_slave_port = piobus.master
232
233    ruby._cpu_ports = cpu_sequencers
234    ruby.num_of_sequencers = len(cpu_sequencers)
235    ruby.random_seed    = options.random_seed
236
237def send_evicts(options):
238    # currently, 2 scenarios warrant forwarding evictions to the CPU:
239    # 1. The O3 model must keep the LSQ coherent with the caches
240    # 2. The x86 mwait instruction is built on top of coherence invalidations
241    if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86':
242        return True
243    return False
244
245    # Create a backing copy of physical memory in case required
246    if options.access_backing_store:
247        ruby.phys_mem = SimpleMemory(range=AddrRange(options.mem_size),
248                                     in_addr_map=False)
249